Abstract: A programmable logic device (PLD) and method for fabricating the PLD are disclosed. The PLD includes an array of PLD cells. Each PLD cell may include a programmable transistor and a select transistor. The PLD array is divided into at least one first area and at least one second area adjacent the at least one first area. The at least one first area includes the programmable transistors and the at least one second area includes the select transistors.

Abstract: A programmable logic device (PLD) and method for fabricating the PLD are disclosed. The PLD includes an array of PLD cells. Each PLD cell may include a programmable transistor and a select transistor. The PLD array is divided into at least one first area and at least one second area adjacent the at least one first area. The at least one first area includes the programmable transistors and the at least one second area includes the select transistors.

Abstract: A method and circuit are disclosed for replacing defective columns of flash memory cells in a flash memory device. The circuit includes a plurality of sets of storage elements, each set of storage elements being capable of identifying a single addressed column of memory cells is to be replaced or a main column line and regular columns of memory cells associated therewith to be replaced. In the event a main column line and the associated regular columns are identified for replacement by a set of storage elements, the set additionally indicates whether the regular columns are regular columns in a single block of memory cells or multiple blocks. Redundancy circuitry performs the replacement operation during a memory access operation based upon the information stored in the sets of storage elements.

Abstract: A method and circuit are disclosed for replacing defective columns of flash memory cells in flash memory device. The circuit includes a plurality of sets of storage elements, each set of storage elements being capable of identifying at least one column of memory cells in any block of memory cells as being defective. The circuit further includes control circuitry for replacing an addressed column of memory cells with a redundant column of memory cells upon an affirmative determination that a set of storage elements identifies the addressed column of memory cells as being defective.

Abstract: A user configurable dual bank memory device is disclosed. The memory device includes a plurality of core banks of memory cells and a set of storage elements having stored therein configuration information. The configuration may be used to configure or group core banks of memory cells together to form a dual bank memory device. The memory device includes control circuitry for preventing a memory read operation from being completed in a core bank or user-configured dual bank in which an ongoing memory modify (program or erase) operation is being performed. The memory device further includes a first set of sense amplifiers dedicated to performing sense amplification only during memory read operations, and a second set of sense amplifiers dedicated to performing sense amplification only during memory modify operations.

Abstract: A user configurable dual bank memory device is disclosed. The memory device includes a plurality of core banks of memory cells and a set of storage elements having stored therein configuration information. The configuration may be used to configure or group core banks of memory cells together to form a dual bank memory device. The memory device includes control circuitry for preventing a memory read operation from being completed in a core bank or user-configured dual bank in which an ongoing memory modify (program or erase) operation is being performed. The memory device further includes a first set of sense amplifiers dedicated to performing sense amplification only during memory read operations, and a second set of sense amplifiers dedicated to performing sense amplification only during memory modify operations.

Abstract: A method and circuit are disclosed for replacing defective columns of flash memory cells in a flash memory device. The circuit includes a plurality of sets of storage elements, each set of storage elements being capable of identifying at least one column of memory cells in any block of memory cells as being defective. The circuit further includes control circuitry for replacing an addressed column of memory cells with a redundant column of memory cells upon an affirmative determination that a set of storage elements identifies the addressed column of memory cells as being defective.

Abstract: A method and circuit are disclosed for replacing defective columns of flash memory cells in a flash memory device. The circuit includes a plurality of sets of storage elements, each set of storage elements being capable of identifying a single addressed column of memory cells is to be replaced or a main column line and regular columns of memory cells associated therewith to be replaced. In the event a main column line and the associated regular columns are identified for replacement by a set of storage elements, the set additionally indicates whether the regular columns are regular columns in a single block of memory cells or multiple blocks. Redundancy circuitry performs the replacement operation during a memory access operation based upon the information stored in the sets of storage elements.

Abstract: A method and circuit are disclosed for providing sector protection to sectors of nonvolatile memory cells in a nonvolatile memory device. The circuit includes maintaining sector protection information in the core of memory cells in the nonvolatile memory device. In this way, the circuitry and/or algorithms utilized for reading and modifying memory cells in the memory cell core that maintain the sector protection information is the same utilized for reading and modifying the other memory cells in the core.