Patents by Inventor Luca Laurin
Luca Laurin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240064990Abstract: A method of forming a microelectronic device comprises forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material. First contact structures are formed to extend through the memory array region and into the alignment mark structures. A support structure is formed over the memory array region. A portion of the base structure is removed to expose the alignment mark structures. A control logic region is formed vertically adjacent a remaining portion of the base structure. The control logic region comprises control logic devices in electrical communication with the first contact structures by way of second contact structures extending partially through the alignment mark structures and contacting the first contact structures. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.Type: ApplicationFiled: November 1, 2023Publication date: February 22, 2024Inventors: Umberto Maria Meotto, Emilio Camerienghi, Paolo Tessariol, Luca Laurin
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Patent number: 11848048Abstract: Methods, systems, and devices for memory device decoder configurations are described. A memory device may include an array of memory cells and decoder circuits. The array may include one or more memory cells coupled with an access line, and a decoder circuit may be configured to bias the access line to one or more voltages. The decoder circuit may include a first transistor coupled with the access line and a second transistor coupled with the access line. The first transistor may be a planar transistor having a first gate electrode formed on a substrate, and the second transistor may be a trench transistor having a second gate electrode that extends into a cavity of the substrate, where a length of a first gate electrode may be greater than a length of the second gate electrode.Type: GrantFiled: November 30, 2021Date of Patent: December 19, 2023Assignee: Micron Technology, Inc.Inventors: Ahmed Nayaz Noemaun, Chandra S. Danana, Durga P. Panda, Luca Laurin, Michael J. Irwin, Rekha Chithra Thomas, Sara Vigano, Stephen W. Russell, Zia A. Shafi
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Patent number: 11818893Abstract: A method of forming a microelectronic device comprises forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material. First contact structures are formed to extend through the memory array region and into the alignment mark structures. A support structure is formed over the memory array region. A portion of the base structure is removed to expose the alignment mark structures. A control logic region is formed vertically adjacent a remaining portion of the base structure. The control logic region comprises control logic devices in electrical communication with the first contact structures by way of second contact structures extending partially through the alignment mark structures and contacting the first contact structures. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.Type: GrantFiled: August 11, 2022Date of Patent: November 14, 2023Inventors: Umberto Maria Meotto, Emilio Camerlenghi, Paolo Tessariol, Luca Laurin
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Patent number: 11790991Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.Type: GrantFiled: August 15, 2022Date of Patent: October 17, 2023Assignee: Micron Technology, Inc.Inventors: Albert Fayrushin, Augusto Benvenuti, Akira Goda, Luca Laurin, Haitao Liu
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Publication number: 20230170015Abstract: Methods, systems, and devices for memory device decoder configurations are described. A memory device may include an array of memory cells and decoder circuits. The array may include one or more memory cells coupled with an access line, and a decoder circuit may be configured to bias the access line to one or more voltages. The decoder circuit may include a first transistor coupled with the access line and a second transistor coupled with the access line. The first transistor may be a planar transistor having a first gate electrode formed on a substrate, and the second transistor may be a trench transistor having a second gate electrode that extends into a cavity of the substrate, where a length of a first gate electrode may be greater than a length of the second gate electrode.Type: ApplicationFiled: November 30, 2021Publication date: June 1, 2023Inventors: Ahmed Nayaz Noemaun, Chandra S. Danana, Durga P. Panda, Luca Laurin, Michael J. Irwin, Rekha Chithra Thomas, Sara Vigano, Stephen W. Russell, Zia A. Shafi
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Publication number: 20220392914Abstract: A method of forming a microelectronic device comprises forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material. First contact structures are formed to extend through the memory array region and into the alignment mark structures. A support structure is formed over the memory array region. A portion of the base structure is removed to expose the alignment mark structures. A control logic region is formed vertically adjacent a remaining portion of the base structure. The control logic region comprises control logic devices in electrical communication with the first contact structures by way of second contact structures extending partially through the alignment mark structures and contacting the first contact structures. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.Type: ApplicationFiled: August 11, 2022Publication date: December 8, 2022Inventors: Umberto Maria Meotto, Emilio Camerlenghi, Paolo Tessariol, Luca Laurin
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Publication number: 20220392533Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.Type: ApplicationFiled: August 15, 2022Publication date: December 8, 2022Inventors: Albert Fayrushin, Augusto Benvenuti, Akira Goda, Luca Laurin, Haitao Liu
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Publication number: 20220367714Abstract: Some embodiments include an integrated assembly having a first gate operatively adjacent a channel region, a first source/drain region on a first side of the channel region, and a second source/drain region on an opposing second side of the channel region. The first source/drain region is spaced from the channel region by an intervening region. The first and second source/drain regions are gatedly coupled to one another through the channel region. A second gate is adjacent a segment of the intervening region and is spaced from the first gate by an insulative region. A lightly-doped region extends across the intervening region and is under at least a portion of the first source/drain region. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: July 19, 2022Publication date: November 17, 2022Applicant: Micron Technology, Inc.Inventors: Zia A. Shafi, Luca Laurin, Durga P. Panda, Sara Vigano'
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Patent number: 11430888Abstract: Some embodiments include an integrated assembly having a first gate operatively adjacent a channel region, a first source/drain region on a first side of the channel region, and a second source/drain region on an opposing second side of the channel region. The first source/drain region is spaced from the channel region by an intervening region. The first and second source/drain regions are gatedly coupled to one another through the channel region. A second gate is adjacent a segment of the intervening region and is spaced from the first gate by an insulative region. A lightly-doped region extends across the intervening region and is under at least a portion of the first source/drain region. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: July 2, 2020Date of Patent: August 30, 2022Assignee: Micron Technology, Inc.Inventors: Zia A. Shafi, Luca Laurin, Durga P. Panda, Sara Vigano´
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Patent number: 11417676Abstract: A method of forming a microelectronic device comprises forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material. First contact structures are formed to extend through the memory array region and into the alignment mark structures. A support structure is formed over the memory array region. A portion of the base structure is removed to expose the alignment mark structures. A control logic region is formed vertically adjacent a remaining portion of the base structure. The control logic region comprises control logic devices in electrical communication with the first contact structures by way of second contact structures extending partially through the alignment mark structures and contacting the first contact structures. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.Type: GrantFiled: August 24, 2020Date of Patent: August 16, 2022Assignee: Micron Technology, Inc.Inventors: Umberto Maria Meotto, Emilio Camerlenghi, Paolo Tessariol, Luca Laurin
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Patent number: 11417396Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.Type: GrantFiled: October 9, 2020Date of Patent: August 16, 2022Assignee: Micron Technology, Inc.Inventors: Albert Fayrushin, Augusto Benvenuti, Akira Goda, Luca Laurin, Haitao Liu
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Publication number: 20220059559Abstract: A method of forming a microelectronic device comprises forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material. First contact structures are formed to extend through the memory array region and into the alignment mark structures. A support structure is formed over the memory array region. A portion of the base structure is removed to expose the alignment mark structures. A control logic region is formed vertically adjacent a remaining portion of the base structure. The control logic region comprises control logic devices in electrical communication with the first contact structures by way of second contact structures extending partially through the alignment mark structures and contacting the first contact structures. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.Type: ApplicationFiled: August 24, 2020Publication date: February 24, 2022Inventors: Umberto Maria Meotto, Emilio Camerlenghi, Paolo Tessariol, Luca Laurin
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Publication number: 20220005950Abstract: Some embodiments include an integrated assembly having a first gate operatively adjacent a channel region, a first source/drain region on a first side of the channel region, and a second source/drain region on an opposing second side of the channel region. The first source/drain region is spaced from the channel region by an intervening region. The first and second source/drain regions are gatedly coupled to one another through the channel region. A second gate is adjacent a segment of the intervening region and is spaced from the first gate by an insulative region. A lightly-doped region extends across the intervening region and is under at least a portion of the first source/drain region. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: July 2, 2020Publication date: January 6, 2022Applicant: Micron Technology, Inc.Inventors: Zia A. Shafi, Luca Laurin, Durga P. Panda, Sara Viganò
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Publication number: 20210027839Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.Type: ApplicationFiled: October 9, 2020Publication date: January 28, 2021Inventors: Albert Fayrushin, Augusto Benvenuti, Akira Goda, Luca Laurin, Haitao Liu
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Patent number: 10803948Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.Type: GrantFiled: November 7, 2018Date of Patent: October 13, 2020Assignee: Micron Technology, Inc.Inventors: Albert Fayrushin, Augusto Benvenuti, Akira Goda, Luca Laurin, Haitao Liu
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Publication number: 20200143884Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.Type: ApplicationFiled: November 7, 2018Publication date: May 7, 2020Inventors: Albert Fayrushin, Augusto Benvenuti, Akira Goda, Luca Laurin, Haitao Liu
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Patent number: 8889520Abstract: Some embodiments include methods of forming BJTs. A first type doped region is formed within semiconductor material. First and second trenches are formed within the semiconductor material to pattern an array of pedestals, and the trenches are filled with electrically insulative material. An upper portion of the first type doped region is counter-doped to form a first stack having a second type doped region over a first type doped region, and an upper portion of the first stack is then counter-doped to form a second stack having a second type doped region between a pair of first type doped regions. Some embodiments include a BJT array. A base implant region is between a pair of emitter/collector implant regions. Electrically insulative material is adjacent the base implant region, and contains at least about 7×1016 atoms/cm3 of base implant region dopant.Type: GrantFiled: May 23, 2014Date of Patent: November 18, 2014Assignee: Micron Technology, Inc.Inventors: Federica Ottogalli, Luca Laurin
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Publication number: 20140273390Abstract: Some embodiments include methods of forming BJTs. A first type doped region is formed within semiconductor material. First and second trenches are formed within the semiconductor material to pattern an array of pedestals, and the trenches are filled with electrically insulative material. An upper portion of the first type doped region is counter-doped to form a first stack having a second type doped region over a first type doped region, and an upper portion of the first stack is then counter-doped to form a second stack having a second type doped region between a pair of first type doped regions. Some embodiments include a BJT array. A base implant region is between a pair of emitter/collector implant regions. Electrically insulative material is adjacent the base implant region, and contains at least about 7×1016 atoms/cm3 of base implant region dopant.Type: ApplicationFiled: May 23, 2014Publication date: September 18, 2014Applicant: Micron Technology, Inc.Inventors: Federica Ottogalli, Luca Laurin
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Publication number: 20140269046Abstract: Methods and devices for selection and/or isolation of memory cells include use of a thyristor For example, a memory storage component may be selected for access, at least in part, by initiating application of a triggering potential to affect a gate of a thyristor that is coupled in series with a memory storage component. The gate of the thyristor connects to a memory cell word line and permits an efficient polarity scheme for selected and unselected memory array conductors to reduce leakage current relative to conventional selectors, such as bipolar junction transistors.Type: ApplicationFiled: November 12, 2013Publication date: September 18, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Luca Laurin, Augusto Benvenuti, Marco Riva
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Patent number: 8766235Abstract: Some embodiments include methods of forming BJTs. A first type doped region is formed within semiconductor material. First and second trenches are formed within the semiconductor material to pattern an array of pedestals, and the trenches are filled with electrically insulative material. An upper portion of the first type doped region is counter-doped to form a first stack having a second type doped region over a first type doped region, and an upper portion of the first stack is then counter-doped to form a second stack having a second type doped region between a pair of first type doped regions. Some embodiments include a BJT array. A base implant region is between a pair of emitter/collector implant regions. Electrically insulative material is adjacent the base implant region, and contains at least about 7×1016 atoms/cm3 of base implant region dopant.Type: GrantFiled: March 8, 2012Date of Patent: July 1, 2014Assignee: Micron Technology, Inc.Inventors: Federica Ottogalli, Luca Laurin