Patents by Inventor Luca Magagni
Luca Magagni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8238502Abstract: A communication system includes first and second independently clocked devices, comprising, for each device, a transmitter and a receiver connected to each other in a crossed way in correspondence of an inter-chip communication channel. The communication system further comprises a synchronizer in turn including at least a first and a second synchronization block, having respective input terminals connected to the receivers and respective output terminals connected to the transmitters and comprising at least: a test pattern generator that generates a programmable test pattern signal; a pattern detector to check a matching between stored and received test pattern signals and thus lock corresponding clock phases of the synchronization blocks in case of positive result of this check; and a delay block able to change the clock phases until a synchronized condition of the synchronization blocks is verified, this synchronized condition corresponding to a matching between stored and received test pattern signals.Type: GrantFiled: December 29, 2008Date of Patent: August 7, 2012Assignee: STMicroelectronics S.r.l.Inventors: Luca Magagni, Luca Ciccarelli, Alberto Fazzi, Roberto Canegallo, Roberto Guerrieri
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Patent number: 7821293Abstract: An embodiment of the present invention relates to a asynchronous interconnection system comprising a transmitter circuit and a receiver circuit inserted between inserted between respective first and second voltage references and having respective transmitter and receiver nodes coupled in a capacitive manner. The receiver circuit comprises: a recovery stage inserted between the first and second voltage references of the receiver circuit and connected to the receiver node; and a state control stage, in turn inserted between the first and second voltage references of the receiver circuit connected to the recovery stage correspondence with a first feedback node providing a first control signal and having a second feedback node connected in a feedback manner to the recovery stage.Type: GrantFiled: December 28, 2007Date of Patent: October 26, 2010Assignee: STMicroelectronics, S.r.l.Inventors: Alberto Fazzi, Luca Ciccarelli, Luca Magagni, Roberto Canegallo, Roberto Guerrieri
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Patent number: 7808276Abstract: Embodiments of the invention relate to a chip-to-chip communication system including a transmitter and a receiver connected to receive respective transmitter and receiver clock signals. The transmitter includes precharge and evaluation blocks connected to each other and to a transmitter clock terminal. The receiver includes a precharge block connected to a receiver clock terminal. The precharge blocks precharge an output terminal of the transmitter and an input terminal of the receiver, respectively, to a value corresponding to a first voltage reference during a low phase of the transmitter clock signal.Type: GrantFiled: September 11, 2006Date of Patent: October 5, 2010Assignee: STMicroelectronics S.R.L.Inventors: Luca Ciccarelli, Luca Magagni, Alberto Fazzi, Roberto Canegallo, Roberto Guerrieri
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Patent number: 7772888Abstract: A communication system for the connection between timing non-correlated synchronous devices comprising at least one transmitter and one receiver inserted between a first and a second voltage reference and connected to each other through a transmission channel in correspondence with respective transmitting and receiving terminals Advantageously, the receiver comprises at least one asynchronous input stage suitable for receiving on the receiving terminal a datum and associated with a synchronous output stage suitable for transmitting this datum in a synchronized way with a clock signal on a synchronized receiving terminal. A method transmits a datum from a transmitter to a receiver interconnected by a capacitive channel in a communication system for the connection between independently clocked devices.Type: GrantFiled: December 29, 2008Date of Patent: August 10, 2010Assignee: STMicroelectronics S.r.l.Inventors: Luca Ciccarelli, Luca Magagni, Alberto Fazzi, Roberto Canegallo, Roberto Guerrieri
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Publication number: 20090168938Abstract: A communication system for the connection between timing non-correlated synchronous devices comprising at least one transmitter and one receiver inserted between a first and a second voltage reference and connected to each other through a transmission channel in correspondence with respective transmitting and receiving terminals Advantageously, the receiver comprises at least one asynchronous input stage suitable for receiving on the receiving terminal a datum and associated with a synchronous output stage suitable for transmitting this datum in a synchronized way with a clock signal on a synchronized receiving terminal. A method transmits a datum from a transmitter to a receiver interconnected by a capacitive channel in a communication system for the connection between independently clocked devices.Type: ApplicationFiled: December 29, 2008Publication date: July 2, 2009Applicant: STMICROELECTRONICS S.R.L.Inventors: Luca Ciccarelli, Luca Magagni, Alberto Fazzi, Roberto Canegallo, Roberto Guerrieri
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Publication number: 20090168860Abstract: A communication system includes first and second independently clocked devices, comprising, for each device, a transmitter and a receiver connected to each other in a crossed way in correspondence of an inter-chip communication channel. The communication system further comprises a synchronizer in turn including at least a first and a second synchronization block, having respective input terminals connected to the receivers and respective output terminals connected to the transmitters and comprising at least: a test pattern generator that generates a programmable test pattern signal; a pattern detector to check a matching between stored and received test pattern signals and thus lock corresponding clock phases of the synchronization blocks in case of positive result of this check; and a delay block able to change the clock phases until a synchronized condition of the synchronization blocks is verified, this synchronized condition corresponding to a matching between stored and received test pattern signals.Type: ApplicationFiled: December 29, 2008Publication date: July 2, 2009Applicant: STMICROELECTRONICS S.R.L.Inventors: Luca Magagni, Luca Ciccarelli, Alberto Fazzi, Roberto Canegallo, Roberto Guerrieri
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Patent number: 7463067Abstract: A switch block for FPGA architectures combining hardware and software techniques in order to reduce both active and standby leakage power.Type: GrantFiled: October 2, 2006Date of Patent: December 9, 2008Assignee: STMicroelectronics S.r.l.Inventors: Luca Ciccarelli, Andrea Lodi, Roberto Giansante, Luca Magagni, Roberto Canegallo, Roberto Guerrieri
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Patent number: 7456637Abstract: An embodiment of the present invention relates to a alignment measurement system for measuring alignment between a plurality of chips of a device, the chips being assembled in a three-dimensional stacking configuration and equipped with at least an integrated capacitive sensor, including a multiple-capacitor structure integrated in the capacitive sensor, at least a sensing circuit connected to the multiple-capacitor structure which issues an output voltage, proportional to a variation of a capacitive value of the multiple-capacitor structure of the integrated capacitive sensor of the device and corresponding to a measured misalignment between the chips of the device.Type: GrantFiled: September 11, 2006Date of Patent: November 25, 2008Assignee: STMicroelectronics, S.r.l.Inventors: Roberto Canegallo, Mauro Mirandola, Alberto Fazzi, Luca Magagni, Roberto Guerrieri
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Publication number: 20080225987Abstract: An embodiment of the present invention relates to a asynchronous interconnection system comprising a transmitter circuit and a receiver circuit inserted between inserted between respective first and second voltage references and having respective transmitter and receiver nodes coupled in a capacitive manner. The receiver circuit comprises: a recovery stage inserted between the first and second voltage references of the receiver circuit and connected to the receiver node; and a state control stage, in turn inserted between the first and second voltage references of the receiver circuit connected to the recovery stage correspondence with a first feedback node providing a first control signal and having a second feedback node connected in a feedback manner to the recovery stage.Type: ApplicationFiled: December 28, 2007Publication date: September 18, 2008Applicant: STMICROELECTRONICS S.r.l.Inventors: Alberto Fazzi, Luca Ciccarelli, Luca Magagni, Roberto Canegallo, Roberto Guerrieri
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Publication number: 20070092011Abstract: Embodiments of the invention relate to a chip-to-chip communication system including a transmitter and a receiver connected to receive respective transmitter and receiver clock signals. The transmitter includes precharge and evaluation blocks connected to each other and to a transmitter clock terminal. The receiver includes a precharge block connected to a receiver clock terminal. The precharge blocks precharge an output terminal of the transmitter and an input terminal of the receiver, respectively, to a value corresponding to a first voltage reference during a low phase of the transmitter clock signal.Type: ApplicationFiled: September 11, 2006Publication date: April 26, 2007Inventors: Luca Ciccarelli, Luca Magagni, Alberto Fazzi, Roberto Canegallo, Roberto Guerrieri
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Publication number: 20070085563Abstract: A switch block for FPGA architectures combining hardware and software techniques in order to reduce both active and standby leakage power.Type: ApplicationFiled: October 2, 2006Publication date: April 19, 2007Applicant: STMicroelectronics S.r.l.Inventors: Luca Ciccarelli, Andrea Lodi, Roberto Giansante, Luca Magagni, Roberto Canegallo, Roberto Guerrieri
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Publication number: 20070067115Abstract: An embodiment of the present invention relates to a alignment measurement system for measuring alignment between a plurality of chips of a device, the chips being assembled in a three-dimensional stacking configuration and equipped with at least an integrated capacitive sensor, comprising a multiple-capacitor structure integrated in said capacitive sensor, at least a sensing circuit connected to said multiple-capacitor structure which issues an output voltage, proportional to a variation of a capacitive value of the multiple-capacitor structure of the integrated capacitive sensor of the device and corresponding to a measured misalignment between the chips of the device.Type: ApplicationFiled: September 11, 2006Publication date: March 22, 2007Inventors: Roberto Canegallo, Mauro Mirandola, Alberto Fazzi, Luca Magagni, Roberto Guerrieri