Abstract: The present invention relates to a stackable, nestable or both stackable and nestable box composed of a front panel, a rear panel and two side panels. The side panels each have a side rest surface comprising at least one guide tooth configured to realise a side centring of an upper box during the realisation of a stacking configuration. There is also preferably provided a retaining tooth capable of preventing sliding, along the front and rear panels, between two stacked boxes. There is also preferably provided a rear panel comprising a step for providing a vertical support of an upper box when stacked. Preferably, there is provided a locking tooth capable of preventing a sliding, along the side panels, between two stacked boxes.

Abstract: Support (1) for tools (U) comprising at least one modular component (2) comprising a main body (3) configured to realize a rest and/or a stop for a tool (U). The main body (3) is further configured to realize a reversible connection between the modular component (2) and one or more further modular components (2).

Abstract: Support (1) for tools (U) comprising at least one modular component (2) comprising a main body (3) configured to realize a rest and/or a stop for a tool (U). The main body (3) is further configured to realize a reversible connection between the modular component (2) and one or more further modular components (2).

Abstract: A non-volatile memory includes cells arranged in rows and columns. Each memory cell includes an access portion and a control portion. The access and control portions share an electrically floating layer of conductive material defining a first capacitive coupling with the access portion and a second capacitive coupling with the control portion. The first capacitive coupling defines a first capacity lower than a second capacity defined by the second capacitive coupling. The control portion is configured so that an electric current extracts charge carriers from the electrically floating layer through Fowler-Nordheim tunneling to store a first logic value in the memory cell. The access portion is configured so that an electric current injects charge carriers in the electrically floating layer by injection of band-to-band tunneling-induced hot electrons to store a second logic value, respectively, in the memory cell.

Abstract: An antifuse cell includes an antifuse capacitor that is activatable with a breakdown voltage to provide an electrically conductive path through the capacitor. A pull-up transistor is coupled to the antifuse capacitor. A current path of the pull-up transistor is arranged in parallel with the antifuse capacitor. A shooting transistor is coupled to the pull-up transistor with the current paths of the pull-up transistor and a current path of the shooting transistor cascaded to each other.

Abstract: Method of protecting a distribution network with a line interconnecting busbars, each busbar being connectable, by means of switching devices adjacent to the busbar, to the line and to loads and/or generators. The method divides the distribution network in multiple protection areas, each comprises a busbar, a protection device and an area controller. Upon a change in connect status of a distribution feeder line, load or generator connectable to one of the busbar, the logic controller in this protection area re-calculates the short circuit level of the areas. Based on the recalculated short circuit levels, the protection settings of the areas may be adapted. The embodiment also provides a system and computer program product adapted to perform the method.

Abstract: An antifuse cell includes an antifuse capacitor that is activatable with a breakdown voltage to provide an electrically conductive path through the capacitor. A pull-up transistor is coupled to the antifuse capacitor. A current path of the pull-up transistor is arranged in parallel with the antifuse capacitor. A shooting transistor is coupled to the pull-up transistor with the current paths of the pull-up transistor and a current path of the shooting transistor cascaded to each other.

Abstract: Method of protecting a distribution network with a line interconnecting busbars, each busbar being connectable, by means of switching devices adjacent to the busbar, to the line and to loads and/or generators. The method divides the distribution network in multiple protection areas, each comprises a busbar, a protection device and an area controller. Upon a change in connect status of a distribution feeder line, load or generator connectable to one of the busbar, the logic controller in this protection area re-calculates the short circuit level of the areas. Based on the recalculated short circuit levels, the protection settings of the areas may be adapted. The embodiment also provides a system and computer program product adapted to perform the method.

Abstract: A non-volatile memory includes memory cells arranged in rows and columns. Each memory cell includes a program/read portion and an erase portion that share an electrically floating layer of conductive material defining a first capacitive coupling with the program/read portion and a second capacitive coupling with the erase portion. The first capacitive coupling defines a first capacitance greater than a second capacitance defined by the second capacitive coupling. The erase portion is configured so that an electric current extracts charge carriers from the electrically floating layer to store a first logic value in the memory cell. The program/read portion is further configured so that an electric current injects charge carriers in the electrically floating layer to store a second logic value in the memory cell.

Abstract: A non-volatile memory includes a plurality of memory cells arranged in a plurality of rows and columns. Each memory cell includes a read portion and a control portion. The read portion and the control portion share an electrically floating layer of conductive material defining a first capacitive coupling with the read portion and a second capacitive coupling with the control portion. The first capacitive coupling defines a first capacity greater than a second capacity defined by the second capacitive coupling. The control portion is configured so that an electric current injects or extracts charge carriers into or from the electrically floating layer to store of a first logic value or a second logic value, respectively, in the memory cell.

Abstract: A non-volatile memory includes memory cells arranged in rows and columns. Each memory cell includes a program/read portion and an erase portion that share an electrically floating layer of conductive material defining a first capacitive coupling with the program/read portion and a second capacitive coupling with the erase portion. The first capacitive coupling defines a first capacitance greater than a second capacitance defined by the second capacitive coupling. The erase portion is configured so that an electric current extracts charge carriers from the electrically floating layer to store a first logic value in the memory cell. The program/read portion is further configured so that an electric current injects charge carriers in the electrically floating layer to store a second logic value in the memory cell.

Abstract: A non-volatile memory includes cells arranged in rows and columns. Each memory cell includes an access portion and a control portion. The access and control portions share an electrically floating layer of conductive material defining a first capacitive coupling with the access portion and a second capacitive coupling with the control portion. The first capacitive coupling defines a first capacity lower than a second capacity defined by the second capacitive coupling. The control portion is configured so that an electric current extracts charge carriers from the electrically floating layer through Fowler-Nordheim tunneling to store a first logic value in the memory cell. The access portion is configured so that an electric current injects charge carriers in the electrically floating layer by injection of band-to-band tunneling-induced hot electrons to store a second logic value, respectively, in the memory cell.

Abstract: A non-volatile memory includes a plurality of memory cells arranged in a plurality of rows and columns. Each memory cell includes a read portion and a control portion. The read portion and the control portion share an electrically floating layer of conductive material defining a first capacitive coupling with the read portion and a second capacitive coupling with the control portion. The first capacitive coupling defines a first capacity greater than a second capacity defined by the second capacitive coupling. The control portion is configured so that an electric current injects or extracts charge carriers into or from the electrically floating layer to store of a first logic value or a second logic value, respectively, in the memory cell.

Abstract: A closure system for drawer cabinets, comprising locking means (2) with stacked cams (4) and that can be configured in at least a releasing position, in which it enables the opening of a drawer (102), and a locking position, in which it prevents the opening of the drawers (102); activation means (9) that can be activated by means of the command of an operator and that is active on said locking means (2) for moving the locking means (2) between said locking (closed) and releasing (open) positions; and enabling means (15) designed for enabling and disabling movement of the locking means (2) between the locking and releasing positions. The activation means (9) is configured in such a manner as to bring itself automatically from the open position to the closed position within a pre-established interval of time, following release of a command for opening the activation means (9) by the operator.

Abstract: Control circuitry for memory cells is described. In an embodiment, a breakdown detection circuit is described which is arranged to detect abnormally high currents indicative of a defective cell during programming of a memory cell through monitoring the impedance level at a terminal in the breakdown detection circuit. The breakdown detection circuit is connected between the device being programmed and ground and comprises three transistors, at least one of which is capable of withstanding the programming voltage in case of breakdown. Other embodiments describe a flag bit cell design, a memory array and methods of reading and writing from/to that array, and circuitry for biasing a memory word-line for both read and write operations. The embodiments may be used separately or in a combination.

Abstract: A closure system for drawer cabinets, comprising locking means (2) with stacked cams (4) and that can be configured in at least a releasing position, in which it enables the opening of a drawer (102), and a locking position, in which it prevents the opening of the drawers (102); activation means (9) that can be activated by means of the command of an operator and that is active on said locking means (2) for moving the locking means (2) between said locking (closed) and releasing (open) positions; and enabling means (15) designed for enabling and disabling movement of the locking means (2) between the locking and releasing positions. The activation means (9) is configured in such a manner as to bring itself automatically from the open position to the closed position within a pre-established interval of time, following release of a command for opening the activation means (9) by the operator.

Abstract: Control circuitry for memory cells is described. In an embodiment, a breakdown detection circuit is described which is arranged to detect abnormally high currents indicative of a defective cell during programming of a memory cell through monitoring the impedance level at a terminal in the breakdown detection circuit. The breakdown detection circuit is connected between the device being programmed and ground and comprises three transistors, at least one of which is capable of withstanding the programming voltage in case of breakdown. Other embodiments describe a flag bit cell design, a memory array and methods of reading and writing from/to that array, and circuitry for biasing a memory word-line for both read and write operations. The embodiments may be used separately or in a combination.