Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array. The control logic allocates power to one or more prioritized processing threads, of a plurality of processing threads that access the memory array, based on a value of a priority ring counter. The control logic starts a timer in response to detecting allocation of the power to a non-prioritized processing thread of the plurality of processing threads. While the timer is running, the control logic increments the priority ring counter before each power management cycle and prioritizes allocation of the power to the one or more prioritized processing threads located within a subset of the plurality of processing threads corresponding to a value of the priority ring counter.

Abstract: One example of a memory device includes an array of flash memory cells, an array of Dynamic Random Access Memory (DRAM) memory cells, and a controller. The controller is configured to execute first instructions stored in the array of DRAM memory cells to access the array of flash memory cells.

Abstract: One example of a memory device includes an array of flash memory cells, an array of Dynamic Random Access Memory (DRAM) memory cells, and a controller. The controller is configured to execute first instructions stored in the array of DRAM memory cells to access the array of flash memory cells.

Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array. The control logic allocates power to one or more prioritized processing threads, of a plurality of processing threads that access the memory array, based on a value of a priority ring counter. The control logic starts a timer in response to detecting allocation of the power to a non-prioritized processing thread of the plurality of processing threads. While the timer is running, the control logic increments the priority ring counter before each power management cycle and prioritizes allocation of the power to the one or more prioritized processing threads located within a subset of the plurality of processing threads corresponding to a value of the priority ring counter.

Abstract: Control logic on a memory die of a multi-die memory sub-system receives, from a memory sub-system controller, a data burst command indicating an upcoming data burst event and determines an expected current utilization in the memory sub-system during the data burst event. The control logic further determines whether the expected current utilization in the memory sub-system during the data burst event satisfies a threshold criterion and responsive to determining that the expected current utilization in the memory sub-system during the data burst event does not satisfy the threshold criterion, pauses one or more operations being executed by the control logic on the memory die until the expected current utilization in the memory sub-system during the data burst event satisfies the threshold criterion.

Abstract: A memory device includes memory dice, each memory die including: a memory array; a memory to store a data structure; and control logic that includes: multiple processing threads to execute memory access operations on the memory array concurrently; a priority ring counter, the data structure to store an association between a value of the priority ring counter and a subset of the multiple processing threads; a threads manager to increment the value of the priority ring counter before a power management cycle and to identify one or more prioritized processing threads corresponding to the subset of the multiple processing threads; and a peak power manager coupled with the threads manager and to prioritize allocation of power to the one or more prioritized processing threads during the power management cycle.

Abstract: A memory device includes a plurality of memory dies. Each memory die of the plurality of memory dies includes a memory die and control logic, operatively coupled with the memory die, to perform operations including receiving, during a current auxiliary data communication cycle, a token to enable auxiliary data communication, in response to receiving the token, determining whether to communicate auxiliary data via an auxiliary data channel to at least one other memory die of a plurality of memory dies, and in response to determining to communicate the auxiliary data via the auxiliary data channel to the at least one other memory die, causing the auxiliary data to be communicated to the at least one other memory die.

Abstract: A method includes receiving a request to perform a memory access operation, wherein the memory access operation includes a set of sub-operations, selecting a current quantization data structure from a plurality of current quantization data structures, wherein each current quantization data structure of the plurality of current quantization data structures maintains, for each sub-operation of the set of sub-operations, a respective current quantization value reflecting an amount of current that is consumed by the respective sub-operation based on a set of peak power management (PPM) operation parameters, and causing the memory access operation to be performed using PPM based on the current quantization data structure.

Abstract: One example of a memory device includes an array of flash memory cells, an array of Dynamic Random Access Memory (DRAM) memory cells, and a controller. The controller is configured to execute first instructions stored in the array of DRAM memory cells to access the array of flash memory cells.

Abstract: A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and control logic. The control logic comprises a plurality of processing threads to execute memory access operations on the memory array concurrently, a thread selection component to identify one or more processing threads of the plurality of processing threads for a power management cycle of the associated memory die and a power management component to determine an amount of power associated with the one or more processing threads and request the amount of power during the power management cycle.

Abstract: A memory device includes memory dies, a first memory die of the memory dies including a memory array and control logic, operatively coupled with the memory array, to perform peak power management (PPM) operations including receiving a token from another memory die, in response to receiving the token, determining whether to reserve a data window during a token circulation time period having a first size determined based on a common clock signal shared among the memory dies and, in response to determining to reserve the data window, causing the data window to be reserved. The data window has a second size different from the first size determined based on the common clock signal. The operations further include causing a data frame to be generated within the data window. The data frame has a third size determined from the second size and includes current consumption information for the memory device.

Abstract: A processing device in a memory sub-system assigns each of a plurality of memory units associated with one or more memory die of a memory device a unique address by which each of the plurality of memory units is identified. The processing device further sends a multi-unit status command to the memory device, the multi-unit status command specifying a subset of the plurality of memory units using corresponding unique addresses and receives a response to the multi-unit status command, the response comprising a multi-bit value comprising a plurality of bits, wherein each bit of the plurality of bits represents a status of one or more parameters of a plurality of parameters for a corresponding one of the plurality of memory units.

Abstract: A memory device includes memory dice, each memory die including: a memory array; a memory to store a data structure; and control logic that includes: multiple processing threads to execute memory access operations on the memory array concurrently; a priority ring counter, the data structure to store an association between a value of the priority ring counter and a subset of the multiple processing threads; a threads manager to increment the value of the priority ring counter before a power management cycle and to identify one or more prioritized processing threads corresponding to the subset of the multiple processing threads; and a peak power manager coupled with the threads manager and to prioritize allocation of power to the one or more prioritized processing threads during the power management cycle.

Abstract: A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and control logic. The control logic comprises a plurality of processing threads to execute memory access operations on the memory array concurrently, a thread selection component to identify one or more processing threads of the plurality of processing threads for a power management cycle of the associated memory die and a power management component to determine an amount of power associated with the one or more processing threads and request the amount of power during the power management cycle.

Abstract: A processing device in a memory sub-system assigns each of a plurality of memory units associated with one or more memory die of a memory device a unique address by which each of the plurality of memory units is identified. The processing device further sends a multi-unit status command to the memory device, the multi-unit status command specifying a subset of the plurality of memory units using corresponding unique addresses and receives a response to the multi-unit status command, the response comprising a multi-bit value comprising a plurality of bits, wherein each bit of the plurality of bits represents a status of one or more parameters of a plurality of parameters for a corresponding one of the plurality of memory units.

Abstract: Embodiments of the present disclosure may relate to a memory controller that may include a main controller to begin a power down of a non-volatile memory storage during a first time period, while operating in a first voltage range, wherein the main controller is to begin the power down of the non-volatile memory in response to an indication of a voltage level being below a predetermined threshold; and a sequencer to continue the power down of the memory storage during a second time period, while operating within a second voltage range lower than the first voltage range. In some embodiments, the sequencer may include a state machine to perform a discharge sequence, where the state machine includes a micro-action output to output a micro-action command to the memory storage based at least in part on a current state of the state machine. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure may relate to a memory controller that may include a main controller to begin a power down of a non-volatile memory storage during a first time period, while operating in a first voltage range, wherein the main controller is to begin the power down of the non-volatile memory in response to an indication of a voltage level being below a predetermined threshold; and a sequencer to continue the power down of the memory storage during a second time period, while operating within a second voltage range lower than the first voltage range. In some embodiments, the sequencer may include a state machine to perform a discharge sequence, where the state machine includes a micro-action output to output a micro-action command to the memory storage based at least in part on a current state of the state machine. Other embodiments may be described and/or claimed.