Abstract: A VLSI architecture adapted to be implemented in the form of a reusable IP cell and including a motion estimation engine, configured to process a cost function and identify a motion vector which minimizes the cost function, an internal memory configured to store the sets of initial candidate vectors for the blocks of a reference frame, first and second controllers to manage the motion vectors and manage an external frame memory, a reference synchronizer to align, at the input to the estimation engine, the data relevant to the reference blocks with the data relevant to candidate blocks coming from the second controller, and a control unit for timing the units included in the architecture and the external interfacing of the architecture itself.