Abstract: A memory device, containing a first electrode, a second electrode and an oxide layer arranged between the first electrode and the second electrode, is produced. The oxide layer has a first zone and a second zone, with the first zone surrounding or being located on either side of the second zone, with the minimum distance d2 separating the two electrodes on the second zone of the oxide layer being less than the minimum distance d1 separating the two electrodes on the first zone of the oxide layer.

Abstract: A memory device, containing a first electrode, a second electrode and an oxide layer arranged between the first electrode and the second electrode, is produced. The oxide layer has a first zone and a second zone, with the first zone surrounding or being located on either side of the second zone, with the minimum distance d2 separating the two electrodes on the second zone of the oxide layer being less than the minimum distance d1 separating the two electrodes on the first zone of the oxide layer.

Abstract: An electronic chip including an integrated circuit arranged a face of a substrate, and a protection device arranged partially facing the integrated circuit is provided. The protection device includes a capacitor having a first electrode and a second electrode between which a layer of phase change material is disposed changing locally from a first resistive state to a second resistive state different from the first state by penetration of a beam. The first state is an amorphous state wherein the capacitor has a first capacitance and/or a first resistance and the second state is a crystalline state wherein the capacitor has a second capacitance and/or a second resistance different from the first capacitance and first resistance. The protection device is electrically connected to the integrated circuit by at least one of the first or second electrodes so that the integrated circuit measures the resistance and/or capacitance of the capacitor.

Abstract: A method for manufacturing a hybrid non-volatile memory device includes forming first conductive pads; depositing a first conductive layer on a second area of the substrate; etching the first conductive layer to obtain second conductive pads, the second conductive pads having a section at their base smaller than at their top; protecting the upper face of the second conductive pads; oxidizing the substrate so that an insulating material layer covers the upper face of the first conductive pads and sides of the second conductive pads; depositing an oxide layer at the tops of the first conductive pads, resulting in memory elements of a first type supported by the first conductive pads; and forming memory elements of a second type at the tops of the second conductive pads. Each memory element of the second type is supported by one of the second conductive pads.

Abstract: An electronic chip including an integrated circuit arranged a face of a substrate, and a protection device arranged partially facing the integrated circuit is provided. The protection device includes a capacitor having a first electrode and a second electrode between which a layer of phase change material is disposed changing locally from a first resistive state to a second resistive state different from the first state by penetration of a beam. The first state is an amorphous state wherein the capacitor has a first capacitance and/or a first resistance and the second state is a crystalline state wherein the capacitor has a second capacitance and/or a second resistance different from the first capacitance and first resistance. The protection device is electrically connected to the integrated circuit by at least one of the first or second electrodes so that the integrated circuit measures the resistance and/or capacitance of the capacitor.

Abstract: A method for manufacturing a hybrid non-volatile memory device includes forming first conductive pads; depositing a first conductive layer on a second area of the substrate; etching the first conductive layer to obtain second conductive pads, the second conductive pads having a section at their base smaller than at their top; protecting the upper face of the second conductive pads; oxidizing the substrate so that an insulating material layer covers the upper face of the first conductive pads and sides of the second conductive pads; depositing an oxide layer at the tops of the first conductive pads, resulting in memory elements of a first type supported by the first conductive pads; and forming memory elements of a second type at the tops of the second conductive pads Each memory element of the second type is supported by one of the second conductive pads.

Abstract: A method for pre-programming a matrix of resistive non-volatile memory cells, the cells including a dielectric material between two conducting electrodes and being initially in an original resistive state, the dielectric material being electrically modified to bring a cell from the original state to another resistive state wherein the resistance of the cell is at least twice and preferably at least ten times lower than the resistance of the cell in the original state. The method includes, prior to mounting a component containing the matrix on a support, programming the matrix by electrically bringing cells from the original state to the other state, leaving the other cells in their original state, and after mounting the component, applying to all the cells an intermediate voltage, to keep in the original state the cells in this state and returning or keeping to/in another state the cells not in the original state.

Abstract: A method for implementing a system containing at least one memory device including a plurality of non-volatile memory cells each including a phase-change material configured to change state reversibly between at least an amorphous state and a crystalline state having different electrical resistances. The method includes steps of manufacturing the memory cells, including the formation of a layer of a phase-change material having an original amorphous state at the end of the steps of manufacturing the memory cells. The method for implementing the embedded system includes, after the steps of manufacturing the memory cells, at least the following steps: (i) pre-programming the memory device consisting of an electrical recrystallization of a selection of memory cells from their original amorphous state; and (ii) assembling the pre-programmed memory device in the system during which the device is subjected to a temperature of between 240° C. and 300° C.

Abstract: The invention relates to a method for pre-programming a matrix of resistive non-volatile memory cells, with said memory cells comprising a dielectric material positioned between two conducting electrodes, with said memory cells being initially in an original resistive state (original HRS) and the dielectric material being able to be so electrically modified as to bring the memory cell from the original resistive state (original HRS) to at least another resistive state (LRS, programmed HRS) wherein the resistance of the memory cell is at least twice and preferably at least ten times lower than the resistance of the memory cell in the original resistive state (original HRS), at least for a reading voltage interval, characterized in that the method comprises the following steps: prior to mounting a component containing said matrix on a support, programming the matrix by electrically bringing a plurality of cells from the original resistive state (original HRS) to said other resistive state (LRS, programmed H

Abstract: The memory cell includes a memory area which is formed in a phase-change material pattern based on chalcogenide. An electric p/n-type junction is series-connected between electrodes. The p/n junction is formed in a crystalline area by the interface between first and second doped areas of the phase-change material pattern. The memory area is formed in one of the two doped areas, at a distance from the junction.

Abstract: A method for implementing a system containing at least one memory device including a plurality of non-volatile memory cells each including a phase-change material configured to change state reversibly between at least an amorphous state and a crystalline state having different electrical resistances. The method includes steps of manufacturing the memory cells, including the formation of a layer of a phase-change material having an original amorphous state at the end of the steps of manufacturing the memory cells. The method for implementing the embedded system includes, after the steps of manufacturing the memory cells, at least the following steps: (i) pre-programming the memory device consisting of an electrical recrystallization of a selection of memory cells from their original amorphous state; and (ii) assembling the pre-programmed memory device in the system during which the device is subjected to a temperature of between 240° C. and 300° C.

Abstract: The present invention is a non-volatile memory cell containing at least two distinct memory zones, each formed in a resistivity-change material, the memory cell containing at least one heating element for each memory zone, each heating element having at least two ends, one of which is connected to a supply line and the other of which is brought into contact with the resistivity-change material, characterized in that the resistivity-change material is arranged in a single block common to each of the memory zones of the memory cell, so as to create distinct memory zones locally.

Abstract: A method for pre-programming a matrix of resistive non-volatile memory cells, the cells including a dielectric material between two conducting electrodes and being initially in an original resistive state, the dielectric material being electrically modified to bring a cell from the original state to another resistive state wherein the resistance of the cell is at least twice and preferably at least ten times lower than the resistance of the cell in the original state. The method includes, prior to mounting a component containing the matrix on a support, programming the matrix by electrically bringing cells from the original state to the other state, leaving the other cells in their original state, and after mounting the component, applying to all the cells an intermediate voltage, to keep in the original state the cells in this state and returning or keeping to/in another state the cells not in the original state.

Abstract: The invention relates to a method for pre-programming a matrix of resistive non-volatile memory cells, with said memory cells comprising a dielectric material positioned between two conducting electrodes, with said memory cells being initially in an original resistive state (original HRS) and the dielectric material being able to be so electrically modified as to bring the memory cell from the original resistive state (original HRS) to at least another resistive state (LRS, programmed HRS) wherein the resistance of the memory cell is at least twice and preferably at least ten times lower than the resistance of the memory cell in the original resistive state (original HRS), at least for a reading voltage interval, characterized in that the method comprises the following steps: prior to mounting a component containing said matrix on a support, programming the matrix by electrically bringing a plurality of cells from the original resistive state (original HRS) to said other resistive state (LRS, programmed H

Abstract: A non-volatile memory cell including a resistivity change material configured to reversibly change state between at least two stable states having different electrical resistances and conformed such that transformation from one state to another is obtained by controlling the temperature increase or decrease of the resistivity change material, wherein the resistivity change material has an ohmic component Ron-mat defined by the ratio between an increment in the programming voltage Vprog causing an increment in a programming current Iprog, wherein the resistivity change material has a non-ohmic component defined by a maintenance voltage Vh such that Vh is greater than zero when the programming voltage Iprog passes through the resistivity change material (22); and greater than an ohmic voltage equal to Ron-mat×Iprog.

Abstract: A non-volatile memory cell including a resistivity change material configured to reversibly change state between at least two stable states having different electrical resistances and conformed such that transformation from one state to another is obtained by controlling the temperature increase or decrease of the resistivity change material, wherein the resistivity change material has an ohmic component Ron-mat defined by the ratio between an increment in the programming voltage Vprog causing an increment in a programming current Iprog, wherein the resistivity change material has a non-ohmic component defined by a maintenance voltage Vh such that Vh is greater than zero when the programming voltage Iprog passes through the resistivity change material (22); and greater than an ohmic voltage equal to Ron-mat×Iprog.

Abstract: A process of producing a resistivity-change memory cell is described. The process includes a deposition at room temperature, in amorphous state, of a layer of a nitrogen (N)-doped alloy of germanium (Ge) and tellurium (Te) to constitute the resistivity-change material of the memory cell. An annealing is then performed such as to limit the type of re-crystallisation by nucleation starting from the amorphous state of the phase-change material. The material used and the process permit the data retention at high temperature to be significantly improved.

Abstract: The object of the present invention is a non-volatile memory cell (10) containing at least two distinct memory zones (17), each formed in a resistivity-change material (14), the memory cell (10) containing at least one heating element (16) for each memory zone (17), each heating element (16) having at least two ends, one of which is connected to a supply line (V1, V2, . . . , VN) and the other of which is brought into contact with the resistivity-change material (14), characterized in that the resistivity-change material (14) is arranged in a single block (34) common to each of the memory zones (17) of the memory cell (10), so as to create distinct memory zones (17) locally.