Abstract: The application is related to a forward error correction mechanism in an optical coherent communication system (CS) comprising a FEC encoder (FE) and a FEC decoder (FD) on the basis of a low density parity check, LDPC, code. The FEC encoder encodes blocks of client bits into codewords by adding parity bits calculated by applying a FEC code to the client bits. Besides, the FEC decoder decodes each codeword by applying thereto an iterative message-passing algorithm, each iteration of the message-passing algorithm comprising evaluating a parity-check matrix defining the FEC code. At the FEC encoder, the coding rate of the FEC code may be varied by varying the number of client/information bits per codeword and/or the number of parity bits per codeword. At the FEC decoder, the parity-check matrix is evaluated column by column at each iteration of the message-passing algorithm. The decoder may be a belief propagation decoder.

Abstract: It is disclosed an optical coherent receiver comprising a number of decoding blocks configured to implement iterations of a FEC iterative message-passing decoding algorithm. The decoding blocks are distributed into two (or more) parallel chains of cascaded decoding blocks. The receiver also comprises an intermediate circuit interposed between the two parallel chains. The optical coherent receiver is switchable between (i) a first operating mode, in which the intermediate circuit is inactive and the two parallel chains separately implement the FEC message-passing decoding algorithm on respective client channels; and (ii) a second operating mode, in which the intermediate circuit is active and the two parallel chains jointly implement the FEC message-passing decoding algorithm on a same client channel, by cooperating through the intermediate circuit.

Abstract: It is disclosed an optical coherent receiver comprising a number of decoding blocks configured to implement iterations of a FEC iterative message-passing decoding algorithm. The decoding blocks are distributed into two (or more) parallel chains of cascaded decoding blocks. The receiver also comprises an intermediate circuit interposed between the two parallel chains. The optical coherent receiver is switchable between (i) a first operating mode, in which the intermediate circuit is inactive and the two parallel chains separately implement the FEC message-passing decoding algorithm on respective client channels; and (ii) a second operating mode, in which the intermediate circuit is active and the two parallel chains jointly implement the FEC message-passing decoding algorithm on a same client channel, by cooperating through the intermediate circuit.

Abstract: Proposed is a method of decoding a differentially encoded PSK modulated optical data signal carrying FEC encoded data values. The optical signal is corrected by an estimated phase offset. From the corrected signal, respective likelihood values for the FEC encoded data values are derived, using an estimation algorithm which accounts for a differential encoding rule used for differentially encoding the optical signal. The derived likelihood values are limited to a predetermined range of values. From the limited likelihood values, FEC decoded data values are derived, using an algorithm which accounts for a FEC encoding rule used for FEC encoding the FEC encoded data values.

Abstract: Proposed is a method of decoding a differentially encoded PSK modulated optical data signal carrying FEC encoded data values. The optical signal is corrected by an estimated phase offset. From the corrected signal, respective likelihood values for the FEC encoded data values are derived, using an estimation algorithm which accounts for a differential encoding rule used for differentially encoding the optical signal. The derived likelihood values are limited to a predetermined range of values. From the limited likelihood values, FEC decoded data values are derived, using an algorithm which accounts for a FEC encoding rule used for FEC encoding the FEC encoded data values.

Abstract: An optical transmitter for a WDM (Wavelength Division Multiplexing) passive optical network (PON) and a WDM PON comprising such an optical transmitter are disclosed. An optical transmitter comprises first mirror and second mirrors at first end and second ends of a cavity; an optical amplifier positioned within the cavity upstream from the first mirror and for amplifying light polarized in a first polarization plane; an optical waveguide for transmitting light from the optical amplifier to the second mirror and vice versa; a first non-reciprocal polarization rotator upstream of the optical amplifier and downstream of the optical waveguide; and a second non-reciprocal polarization rotator upstream of the optical waveguide and downstream of the first mirror; wherein the first and second non-reciprocal polarization rotators rotate the polarization of the light such that light which re-enters the optical amplifier after having been reflected by the second mirror is polarized in the first polarization plane.

Abstract: Disclosed is a device for providing an improved switching from one of two or more working resources to at least one spare resource in a telecommunication apparatus, each of the working resources comprising a profile with a set of parameters and configuration information, wherein the at least one spare resource comprises a bank of profiles, each profile of the bank corresponding to a profile of the working resources, and further comprises means for selecting a profile of the bank so that when a working resource has to be replaced by a spare resource, a profile in the bank corresponding to the profile of the working resource is selected for provisioning the spare resources accordingly. According to an embodiment, the working and spare resources are embodied in ports of a telecommunication apparatus.

Abstract: Disclosed is a device and method for processing a frame including overhead and payload, the device comprising: a first hardware module for processing the payload, the payload processing comprising termination/adaptation and cross-connection functions; and a second hardware module for processing at least a part of overhead, wherein said second hardware module cooperates with the first hardware module for controlling the payload cross-connection and consequent actions.

Abstract: The present invention provides for a method and apparatus for carrying out connection and related input/output processing functions in a Sinchronous Digital Hierarchy (SDH/SONET) transport node (network), in which the payload switching matrices (e.g. MSPC and HPC matrices for an High Order VC system) collapse into one single functional block (MTRX), while the Virtual Container (VCs) monitoring functions (HVC_RX, HVC_TX) are shifted to the Input/Output position of the matrices.

Abstract: Disclosed is an input port to one or more switching matrices of a network element or the like through a number of backpanel connections, the port receiving input flows in the form of bits arranged in frames, the port comprising: a memory for storing a number of bytes belonging to a tributary; a slicer for slicing the stored bytes in a number of word structures and a backpanel framer for forming backpanel frames with said word structures, the number of said word structures being equal to the number of said switching matrices and the capacity of the input flow being equal to the capacity of the overall backpanel connection capacity.

Abstract: It is disclosed a method of demapping a tributary from a first frame into a second frame, the first frame comprising a plurality of tributary words and a synchronization word, the method comprising: providing a first and a second counters; increasing the first counter by a first value at each clock cycle of the second frame; and performing reading operations according to the second counter. It further comprises: generating synchronization information according to the synchronization word; according to the synchronization information, performing a change of state between a first state and a second state, wherein, in the first state, the second counter is synchronized to the first counter at each clock cycle of the second frame, and in the second state, the second counter is synchronized to the first counter at a predetermined instant of the second frame and the second counter is increased by a second value at each clock cycle of the second frame wherein the reading operation is performed.

Abstract: It is disclosed a mapper for mapping a tributary from a first frame into a second frame. The mapper comprises: a first register for generating a first counter which is adapted to be increased by a first value at each clock cycle of the first frame; a second register for generating a second counter which is adapted to be increased by a second value at each clock cycle of the second frame; a difference module for calculating a phase error between the first counter and the second counter; and a frame generation module, responsive to the phase error, for mapping the tributary into the second frame.

Abstract: A method is disclosed for digitally measuring the phase of a data signal with frequency fx in a transmission network. The method comprises the following steps: providing a counter; increasing the counter upon each occurrence of an event marking the evolution of the data signal with frequency fx and sampling the counter at a first sampling frequency fc, thus obtaining a first sample sequence. According to the method of the invention, the first sample frequency fc is uncorrelated from the frequency fx. The method according to the invention further comprises the steps of sampling the first sample sequence at a second sampling frequency fs, thus obtaining a second sample sequence; and digitally processing said second sample sequence in order to estimate said phase of said data signal. Preferably, said counter is sampled at a frequency fc with fc=?·fx, where ? is an irrational number.

Abstract: Disclosed is a switch device arrangement for a network element cross-connecting incoming signal frames. The said arrangement comprises an input port for receiving signal frames, a first cross-connection stage and a second cross-connection stage connected to said first stage. Each cross-connection stage comprises at least one switch device with, in turn, at least one TDM matrix. According to the present invention, only the input port comprises HPA means for properly modifying the pointers of the signal frames. Furthermore, each switch device is designed for cross-connecting at least one part of the tributaries of the signal frames and generating at its output a delayed reference frame.

Abstract: Disclosed is an input port to one or more switching matrices of a network element or the like through a number of backpanel connections, the port receiving input flows in the form of bits arranged in frames, the port comprising: a memory for storing a number of bytes belonging to a tributary; a slicer for slicing the stored bytes in a number of word structures and a backpanel framer for forming backpanel frames with said word structures, the number of said word structures being equal to the number of said switching matrices and the capacity of the input flow being equal to the capacity of the overall backpanel connection capacity.

Abstract: Disclosed is a device and method for processing a frame including overhead and payload, the device comprising: a first hardware module for processing the payload, the payload processing comprising termination/adaptation and cross-connection functions; and a second hardware module for processing at least a part of overhead, wherein said second hardware module cooperates with the first hardware module for controlling the payload cross-connection and consequent actions.

Abstract: Disclosed is a device for providing an improved switching from one of two or more working resources to at least one spare resource in a telecommunication apparatus, each of the working resources comprising a profile with a set of parameters and configuration information, wherein the at least one spare resource comprises a bank of profiles, each profile of the bank corresponding to a profile of the working resources, and further comprises means for selecting a profile of the bank so that when a working resource has to be replaced by a spare resource, a profile in the bank corresponding to the profile of the working resource is selected for provisioning the spare resources accordingly. According to an embodiment, the working and spare resources are embodied in ports of a telecommunication apparatus.

Abstract: The present invention provides for a method and apparatus for carrying out connection and related input/output processing functions in a Sinchronous Digital Hierarchy (SDH/SONET) transport node (network), in which the payload switching matrices (e.g. MSPC and HPC matrices for an High Order VC system) collapse into one single functional block (MTRX), while the Virtual Container (VCs) monitoring functions (HVC_RX, HVC_TX) are shifted to the Input/Output position of the matrices.

Abstract: A method for improving management of pointer processing for concatenated and/or not concatenated payload in SDH/SONET frames is described. The method comprises the steps of: receiving separate indications about the status of single tributaries, the indications comprising Normal State (NORM), Concatenated State (CONC), Loss of Pointer (LOP) and Alarm Indication Signal (AIS), processing, according to a pure combinatorial logic, the separate indications; and in case one of preset concatenation statuses is identified, such an identified current status of received flow of SDH/SONET frames is promptly declared or, in case no preset concatenation statuses are identified the tributaries are treated as stand alone. Differently from the prior art, the step of declaring a concatenation state is performed independently from a previously stored concatenation level.

Abstract: A method and circuit are described for improving the pointer processing in the case of synchronous digital hierarchy (SDH) or synchronous optical network (SONET) transmission frames with VC4_4c, VC4_16c and VC4_64c concatenated payloads. The technique proposed by the existing Standards provides for two different state diagrams to be used in the pointer processing algorithm. One state diagram is used in the case of a concatenated payload and the other state diagram is used in the case of a non-concatenated payload. However, no solution is disclosed for automatically going from the states of one diagram to the states of the other diagram. The present invention provides a circuit so constructed that it can be used in an apparatus processing STM-4, STM-16 and STM-64 frames, through which the automatic recognition of the VC4-4c, VC4-16c and VC4-64c payload concatenation can be achieved. Therefore, it is not necessary to configure in advance the concatenation or non-concatenation condition.