Abstract: The discriminative clustering technique tests a provided set of Gaussian distributions corresponding to an acoustic vector space. A distance metric, such as the Bhattacharyya distance, is used to assess which distributions are sufficiently proximal to be merged into a new distribution. Merging is accomplished by computing the centroid of the new distribution by minimizing the Bhattacharyya distance between the parameters of the Gaussian distributions being merged.

Abstract: A method and apparatus for data entry by voice under adverse conditions is disclosed. More specifically it provides a way for efficient and robust form filling by voice. A form can typically contain one or several fields that must be filled in. The user communicates to a speech recognition system and word spotting is performed upon the utterance. The spotted words of an utterance form a phrase that can contain field-specific values and/or commands. Recognized values are echoed back to the speaker via a text-to-speech system. Unreliable or unsafe inputs for which the confidence measure is found to be low (e.g. ill-pronounced speech or noises) are rejected by the spotter. Speaker adaptation is furthermore performed transparently to improve speech recognition accuracy. Other input modalities can be additionally supported (e.g. keyboard and touch-screen). The system maintains a dialogue history to enable editing and correction operations on all active fields.

Abstract: The acoustic speech signal is decomposed into wavelets arranged in an asymmetrical tree data structure from which individual nodes may be selected to best extract local features, as needed to model specific classes of sound units. The wavelet packet transformation is smoothed through integration and compressed to apply a non-linearity prior to discrete cosine transformation. The resulting subband features such as cepstral coefficients may then be used to construct the speech recognizer's speech models. Using the local feature information extracted in this manner allows a single recognizer to be optimized for several different classes of sound units, thereby eliminating the need for parallel path recognizers.

Abstract: A method for performing noise adaptation of a target speech signal input to a speech recognition system, where the target speech signal contains both additive and convolutional noises. The method includes estimating an additive noise bias and a convolutional noise bias; in the target speech signal; and jointly compensating the target speech signal for the additive and convolutional noise biases in a feature domain.

Abstract: The speech recognizer incorporates a language model that reduces the number of acoustic pattern matching sequences that must be performed by the recognizer. The language model is based on knowledge of a pre-defined set of syntactically defined content and includes a data structure that organizes the content according to acoustic confusability. A spelled name recognition system based on the recognizer employs a language model based on classes of letters that the recognizer frequently confuses for one another. The language model data structure is optionally an N-gram data structure, a tree data structure, or an incrementally configured network that is built during a training sequence. The incrementally configured network has nodes that are selected based on acoustic distance from a predetermined lexicon.

Abstract: An integrated circuit including two phase-locked loops each with its own oscillator. To prevent locking owing to injection between the two oscillators due to stray currents in the integrated circuit, a noise generator is coupled to the oscillator of one of the loops and a timer is provided for activating the noise generator in a manner such that the noise generated changes the frequency of the oscillator randomly when the other loop is in operation.

Abstract: The circuit is for translating a switching signal disposed between ground level and Vdd to a translated switching signal disposed between first and second voltages Vhsrc and Vhstrap. The circuit includes a bistable circuit formed by two branches which include two nMOS transistors the sources of which are connected to ground and are controlled, respectively, by a switching-on signal and by a switching-off signal derived from the switching signal by means of a buffer and an inverter, respectively. Two pMOS transistors having their sources at the voltage Vhstrap and the drain of one connected to the gate of the other output the translated switching signal at one of their drains. Two further pMOS transistors having gates at the first voltage Vhsrc are interposed between the two nMOS transistors and the two pMOS transistors.

Abstract: Generator of clock pulses having a period selectable between a first period, a second period of greater duration than that of the first period and a third period, with duration imposed by the transitions of a synchronization signal (SYNC) from a first to a second logic level, comprising: a resettable oscillator controlled by a binary selection signal having a first and second logic level, in order to generate periodic pulses having the first or second period depending on the logic level of the said selection signal, the oscillator comprising a pulse extractor triggered by the periodic pulses and by the transitions from first to second logic level of the synchronization signal in order to generate, with each pulse and transition received as input, one of the said periodic clock pulses, acting as reset signal for the oscillator, and a finite state logic machine, having at least two states A, B and inputs for receiving the synchronization signal and the periodic pulses, and generating the selection signal at a f

Abstract: Switching losses in a DC-to-DC converter idling in a pulse-skipping mode are reduced by inhibiting any intervening turn-off command by a PWM control loop of the converter for as long as the current through the inductor of the converter remains below a minimum threshold value set by a dedicated comparator. The method is implemented by employing a comparator with a certain hysteresis and by logically masking the switching to a logic "0" of a high frequency clock (switching) signal of the converter for the entire period of time the current in the inductor remains below the minimum threshold.