Patents by Inventor Luca Zanotti
Luca Zanotti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240067375Abstract: A method to set up at least one movable operating member (5, 7) of an automatic machine (1) for manufacturing consumer articles (3) comprising the steps (16, 17) of: defining a first motion profile (FP) of the movable operating member (5, 7), determining possible imperfections in the processing of the articles (3), defining a corresponding second motion profile (SP) of an electric actuator system (8, 9), which, through a motion transmission system (12), is mechanically connected to the movable operating member (5, 7) and moves the movable operating member (5, 7) with the first motion profile (FP), correcting, by means of an interface device (15) of the automatic machine (1) and based on the possible determined imperfections, at least one conversion parameter (50) concerning the processing on the articles (3) performed by the movable operating member (5, 7); processing the first motion profile (FP), thus obtaining a first modified profile (MFP) of the movable operating member (5, 7).Type: ApplicationFiled: March 9, 2022Publication date: February 29, 2024Inventors: Matteo Degli Esposti, Luca Carboni, Maurizio Zanotti, Giuliano Gamberini
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Patent number: 11871668Abstract: A thermoelectric generator includes a substrate and one or more thermoelectric elements on the substrate and each configured to convert a thermal drop across the thermoelectric elements into an electric potential by Seebeck effect. The thermoelectric generator includes a cavity between the substrate and the thermoelectric elements. The thermoelectric generator includes, within the cavity, a support structure for supporting the thermoelectric elements. The support structure has a thermal conductivity lower than a thermal conductivity of the substrate.Type: GrantFiled: January 26, 2021Date of Patent: January 9, 2024Assignee: STMICROELECTRONICS S.r.l.Inventors: Paolo Ferrari, Flavio Francesco Villa, Luca Zanotti, Andrea Nomellini, Luca Seghizzi
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Publication number: 20230301191Abstract: A method of fabricating a thermoelectric converter that includes providing a layer of a Silicon-based material having a first surface and a second surface, opposite to and separated from the first surface by a Silicon-based material layer thickness; forming a plurality of first thermoelectrically active elements of a first thermoelectric semiconductor material having a first Seebeck coefficient, and forming a plurality of second thermoelectrically active elements of a second thermoelectric semiconductor material having a second Seebeck coefficient, wherein the first and second thermoelectrically active elements are formed to extend through the Silicon-based material layer thickness, from the first surface to the second surface; forming electrically conductive interconnections in correspondence of the first surface and of the second surface of the layer of Silicon-based material, for electrically interconnecting the plurality of first thermoelectrically active elements and the plurality of second thermoelectriType: ApplicationFiled: May 24, 2023Publication date: September 21, 2023Applicant: STMICROELECTRONICS S.r.l.Inventors: Paolo FERRARI, Flavio Francesco VILLA, Lucia ZULLINO, Andrea NOMELLINI, Luca SEGHIZZI, Luca ZANOTTI, Bruno MURARI, Martina SCOLARI
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Patent number: 11696504Abstract: A method of fabricating a thermoelectric converter that includes providing a layer of a Silicon-based material having a first surface and a second surface, opposite to and separated from the first surface by a Silicon-based material layer thickness; forming a plurality of first thermoelectrically active elements of a first thermoelectric semiconductor material having a first Seebeck coefficient, and forming a plurality of second thermoelectrically active elements of a second thermoelectric semiconductor material having a second Seebeck coefficient, wherein the first and second thermoelectrically active elements are formed to extend through the Silicon-based material layer thickness, from the first surface to the second surface; forming electrically conductive interconnections in correspondence of the first surface and of the second surface of the layer of Silicon-based material, for electrically interconnecting the plurality of first thermoelectrically active elements and the plurality of second thermoelectriType: GrantFiled: May 14, 2021Date of Patent: July 4, 2023Assignee: STMICROELECTRONICS S.r.l.Inventors: Paolo Ferrari, Flavio Francesco Villa, Lucia Zullino, Andrea Nomellini, Luca Seghizzi, Luca Zanotti, Bruno Murari, Martina Scolari
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Publication number: 20210359189Abstract: A method of fabricating a thermoelectric converter that includes providing a layer of a Silicon-based material having a first surface and a second surface, opposite to and separated from the first surface by a Silicon-based material layer thickness; forming a plurality of first thermoelectrically active elements of a first thermoelectric semiconductor material having a first Seebeck coefficient, and forming a plurality of second thermoelectrically active elements of a second thermoelectric semiconductor material having a second Seebeck coefficient, wherein the first and second thermoelectrically active elements are formed to extend through the Silicon-based material layer thickness, from the first surface to the second surface; forming electrically conductive interconnections in correspondence of the first surface and of the second surface of the layer of Silicon-based material, for electrically interconnecting the plurality of first thermoelectrically active elements and the plurality of second thermoelectriType: ApplicationFiled: May 14, 2021Publication date: November 18, 2021Applicant: STMICROELECTRONICS S.r.l.Inventors: Paolo FERRARI, Flavio Francesco VILLA, Lucia ZULLINO, Andrea NOMELLINI, Luca SEGHIZZI, Luca ZANOTTI, Bruno MURARI, Martina SCOLARI
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Publication number: 20210242387Abstract: A thermoelectric generator includes a substrate and one or more thermoelectric elements on the substrate and each configured to convert a thermal drop across the thermoelectric elements into an electric potential by Seebeck effect. The thermoelectric generator includes a cavity between the substrate and the thermoelectric elements. The thermoelectric generator includes, within the cavity, a support structure for supporting the thermoelectric elements. The support structure has a thermal conductivity lower than a thermal conductivity of the substrate.Type: ApplicationFiled: January 26, 2021Publication date: August 5, 2021Applicant: STMICROELECTRONICS S.R.L.Inventors: Paolo FERRARI, Flavio Francesco VILLA, Luca ZANOTTI, Andrea NOMELLINI, Luca SEGHIZZI
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Publication number: 20150175410Abstract: A process for manufacturing a micromechanical structure envisages: forming a buried cavity within a body of semiconductor material, separated from a top surface of the body by a first surface layer; and forming an access duct for fluid communication between the buried cavity and an external environment. The method envisages: forming an etching mask on the top surface at a first access area; forming a second surface layer on the top surface and on the etching mask; carrying out an etch such as to remove, in a position corresponding to the first access area, a portion of the second surface layer, and an underlying portion of the first surface layer not covered by the etching mask until the buried cavity is reached, thus forming both the first access duct and a filter element, set between the first access duct and the same buried cavity.Type: ApplicationFiled: December 18, 2013Publication date: June 25, 2015Applicant: STMicroelectronics S.r.l.Inventors: Marco Ferrera, Matteo Perletti, Igor Varisco, Luca Zanotti
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Patent number: 9061248Abstract: A process for manufacturing a micromechanical structure envisages: forming a buried cavity within a body of semiconductor material, separated from a top surface of the body by a first surface layer; and forming an access duct for fluid communication between the buried cavity and an external environment. The method envisages: forming an etching mask on the top surface at a first access area; forming a second surface layer on the top surface and on the etching mask; carrying out an etch such as to remove, in a position corresponding to the first access area, a portion of the second surface layer, and an underlying portion of the first surface layer not covered by the etching mask until the buried cavity is reached, thus forming both the first access duct and a filter element, set between the first access duct and the same buried cavity.Type: GrantFiled: December 18, 2013Date of Patent: June 23, 2015Assignee: STMicroelectronics S.r.l.Inventors: Marco Ferrera, Matteo Perletti, Igor Varisco, Luca Zanotti
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Patent number: 8633553Abstract: A process for manufacturing a micromechanical structure envisages: forming a buried cavity within a body of semiconductor material, separated from a top surface of the body by a first surface layer; and forming an access duct for fluid communication between the buried cavity and an external environment. The method envisages: forming an etching mask on the top surface at a first access area; forming a second surface layer on the top surface and on the etching mask; carrying out an etch such as to remove, in a position corresponding to the first access area, a portion of the second surface layer, and an underlying portion of the first surface layer not covered by the etching mask until the buried cavity is reached, thus forming both the first access duct and a filter element, set between the first access duct and the same buried cavity.Type: GrantFiled: July 25, 2011Date of Patent: January 21, 2014Assignee: STMicroelectronics S.r.l.Inventors: Marco Ferrera, Matteo Perletti, Igor Varisco, Luca Zanotti
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Patent number: 8124865Abstract: A method of fabricating a wafer-size photovoltaic cell module includes defining an integrated cellular structure of a light converting monolateral or bilateral junction diode in an epitaxially grown detachable layer including a first deposited metal current collecting terminal of the diode. The method also includes laminating onto the surface of the processed epitaxially grown detachable layer a film of an optical grade plastic material resistant to hydrofluoric acid solutions. The method further includes immersing the wafer in a hydrofluoric acid solution causing detachment of the epitaxially grown silicon layer laminated with the film, and polishing the surface of separation of the detached epitaxially grown layer and forming a second metal current collecting terminal of the diode by masked deposition of a metal at a temperature tolerable by the film.Type: GrantFiled: November 16, 2005Date of Patent: February 28, 2012Assignee: STMicroelectronics S.R.L.Inventors: Pietro Montanini, Paolo Riboli, Luca Zanotti, Michele Palmieri, Marta Mottura
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Publication number: 20120018819Abstract: A process for manufacturing a micromechanical structure envisages: forming a buried cavity within a body of semiconductor material, separated from a top surface of the body by a first surface layer; and forming an access duct for fluid communication between the buried cavity and an external environment. The method envisages: forming an etching mask on the top surface at a first access area; forming a second surface layer on the top surface and on the etching mask; carrying out an etch such as to remove, in a position corresponding to the first access area, a portion of the second surface layer, and an underlying portion of the first surface layer not covered by the etching mask until the buried cavity is reached, thus forming both the first access duct and a filter element, set between the first access duct and the same buried cavity.Type: ApplicationFiled: July 25, 2011Publication date: January 26, 2012Applicant: STMICROELECTRONICS S.R.L.Inventors: Marco Ferrera, Matteo Perletti, Igor Varisco, Luca Zanotti
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Publication number: 20060118164Abstract: A method of fabricating a wafer-size photovoltaic cell module includes defining an integrated cellular structure of a light converting monolateral or bilateral junction diode in an epitaxially grown detachable layer including a first deposited metal current collecting terminal of the diode. The method also includes laminating onto the surface of the processed epitaxially grown detachable layer a film of an optical grade plastic material resistant to hydrofluoric acid solutions. The method further includes immersing the wafer in a hydrofluoric acid solution causing detachment of the epitaxially grown silicon layer laminated with the film, and polishing the surface of separation of the detached epitaxially grown layer and forming a second metal current collecting terminal of the diode by masked deposition of a metal at a temperature tolerable by the film.Type: ApplicationFiled: November 16, 2005Publication date: June 8, 2006Applicant: STMicroelectronics S.r.l.Inventors: Pietro Montanini, Paolo Riboli, Luca Zanotti, Michele Palmieri, Marta Mottura
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Patent number: 6888225Abstract: A process for forming a final passivation layer over an integrated circuit comprises a step of forming, over a surface of the integrated circuit, a protective film by means of High-Density Plasma Chemical Vapor Deposition.Type: GrantFiled: December 18, 2002Date of Patent: May 3, 2005Assignee: STMicroelectronics S.r.l.Inventors: Giorgio De Santi, Luca Zanotti
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Publication number: 20030122221Abstract: A process for forming a final passivation layer over an integrated circuit comprises a step of forming, over a surface of the integrated circuit, a protective film by means of High-Density Plasma Chemical Vapor Deposition.Type: ApplicationFiled: December 18, 2002Publication date: July 3, 2003Applicant: STMicroelectronics S.r.I.Inventors: Giorgio De Santi, Luca Zanotti
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Patent number: 6531714Abstract: A method for manufacturing a semiconductor device having improved adhesion at an interface between layers of dielectric material, comprising the steps of forming a first layer of dielectric material on at least one part of a structure defined in a semiconductor substrate and forming a second dielectric material layer superimposed on the least one part of the first layer. The method further includes the step of forming, in the part where the first and second layers are superimposed, an intermediate adhesion layer comprising a ternary compound of silicon, oxygen and carbon. The formation of the adhesion layer takes place at low temperature and in an atmosphere kept essentially free of oxidative substances different from those serving to provide the silicon and the carbon to the layer. Preferably the layer is formed by the plasma enhanced chemical vapour deposition technique.Type: GrantFiled: December 14, 1998Date of Patent: March 11, 2003Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Maurizio Bacchetta, Luca Zanotti, Giuseppe Queirolo
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Publication number: 20010017286Abstract: The present invention relates an etch process of a dielectric film deposited on a substrate, characterized by using a chamber of PECVD type having an upper electrode coupled with a RF source and a lower electrode connected to ground on which a silicon substrate is placed. The etch of the dielectric film is obtained by means of a plurality of active gases mixed with at least one conveyance gas so as to obtain a low rate of etch and an uniform etch of said deposited dielectric film.Type: ApplicationFiled: January 11, 2001Publication date: August 30, 2001Inventor: Luca Zanotti
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Publication number: 20010004119Abstract: A non-volatile memory device including memory cells each formed as a MOS transistor having source and drain regions and gate structures is described. The source and drain regions and the gate structures are covered by a silicon nitride layer obtained in a standard PECVD chamber at a temperature lower than 480 ° C. and with a suitable gas flow. An insulated layer is placed over the silicon nitride layer.Type: ApplicationFiled: December 6, 2000Publication date: June 21, 2001Inventors: Alessandra Foraboschi, Luca Zanotti
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Publication number: 20010001727Abstract: A process for forming a final passivation layer over an integrated circuit comprises a step of forming, over a surface of the integrated circuit, a protective film by means of High-Density Plasma Chemical Vapor Deposition.Type: ApplicationFiled: April 14, 1998Publication date: May 24, 2001Inventors: GIORGIO DE SANTI, LUCA ZANOTTI
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Patent number: 6187683Abstract: A planarization method is disclosed to provide improved protection against cracking of the final passivation layer of integrated circuit devices. In one embodiment, such method includes final passivation of an integrated circuit device including at least one integrated circuit chip. Such final passivation includes the step of forming a layer of protective material over a top surface of the integrated circuit chip, and a subsequent step of planarizing such layer of protective material to obtain a protection layer having a substantially flat top surface.Type: GrantFiled: April 14, 1998Date of Patent: February 13, 2001Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Giorgio De Santi, Luca Zanotti, Giuseppe Crisenza
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Patent number: 6153537Abstract: A method for manufacturing a semiconductor device having improved adhesion at an interface between layers of dielectric material, comprising the steps of forming a first layer of dielectric material on at least one part of a structure defined in a semiconductor substrate and forming a second dielectric material layer superimposed on the least one part of the first layer. The method further includes the step of forming, in the part where the first and second layers are superimposed, an intermediate adhesion layer comprising a ternary compound of silicon, oxygen and carbon. The formation of the adhesion layer takes place at low temperature and in an atmosphere kept essentially free of oxidative substances different from those serving to provide the silicon and the carbon to the layer. Preferably the layer is formed by the plasma enhanced chemical vapour deposition technique.Type: GrantFiled: December 22, 1995Date of Patent: November 28, 2000Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Maurizio Bacchetta, Luca Zanotti, Giuseppe Queirolo