Abstract: A sensor includes a sensing element to produce a sensing element signal and a processor responsive to the sensing element signal to generate a sensor output signal comprising a Single Edge Nibble Transmission (SENT) frame. The SENT frame includes a Status and Communication (SCN) nibble comprising a bit 0 and a bit 1 that represent a status of at least one internal diagnostic indicator and a plurality of data nibbles. At least one of the plurality of data nibbles includes a cyclic redundancy check (CRC), the CRC being an encoding of the bit 0 and the bit 1 of the SCN nibble and the plurality of data nibbles and at least one of the plurality of data nibbles includes a count that indicates a new frame, the CRC being at least a five bit value.

Abstract: A sensor includes a sensing element to produce a sensing element signal and a processor responsive to the sensing element signal to generate a sensor output signal comprising a Single Edge Nibble Transmission (SENT) frame. The SENT frame includes a Status and Communication (SCN) nibble comprising a bit 0 and a bit 1 that represent a status of at least one internal diagnostic indicator and a plurality of data nibbles. At least one of the plurality of data nibbles includes a cyclic redundancy check (CRC), the CRC being an encoding of the bit 0 and the bit 1 of the SCN nibble and the plurality of data nibbles and at least one of the plurality of data nibbles includes a count that indicates a new frame, the CRC being at least a five bit value.

Abstract: In one aspect, a magnetic field sensor includes a magnetic field sensing element configured to detect changes in a magnetic field caused by a target and an encoder configured to process signals originating from the magnetic field element. The encoder is configured to generate a first output signal and a second output signal. In a non-fault state, the first and second output signals are 90 electrical degrees out of phase from one another, and in a fault state, the first and second output signals are in phase with each other.

Abstract: A system is provided, comprising: a plurality of flip-flops that are configured to receive a reset signal, each of the plurality of flip-flops having a respective output port, and each of the plurality of flip-flops being configured to assume a respective default state when the reset signal is set to a predetermined value; and a reset monitor circuit that is coupled to the respective output port of each of the plurality of flip-flops, the reset monitor circuit being configured to generate a status signal indicating whether each of the flip-flops has assumed the flip-flop's respective default state after the reset signal is set to the predetermined value, wherein assuming a respective default state by each of the plurality of flip-flops results in a predetermined bit string being stored in the plurality of flip-flops.

Abstract: A system is provided, comprising: a plurality of flip-flops that are configured to receive a reset signal, each of the plurality of flip-flops having a respective output port, and each of the plurality of flip-flops being configured to assume a respective default state when the reset signal is set to a predetermined value; and a reset monitor circuit that is coupled to the respective output port of each of the plurality of flip-flops, the reset monitor circuit being configured to generate a status signal indicating whether each of the flip-flops has assumed the flip-flop's respective default state after the reset signal is set to the predetermined value, wherein assuming a respective default state by each of the plurality of flip-flops results in a predetermined bit string being stored in the plurality of flip-flops.

Abstract: In one aspect, an integrated circuit (IC) includes a multiplexor configured to receive data from a non-volatile memory and configured to receive data from a shadow memory, a shift register configured to generate a first signature from the data received from the non-volatile memory and configured to generate a second signature from the data received from the shadow memory; a signature storage configured to store the first signature; and a shadow memory checking controller configured to enable the multiplexor to send the data from the non-volatile memory to the shift register, and send a command to reload the shadow memory with data from the non-volatile memory in response to receiving an error flag. The IC also includes a comparator circuit configured to compare the first signature and the second signature and configured to send the error flag in response to the first signature and the second signature being different.

Abstract: In one aspect, an integrated circuit (IC) includes a multiplexor configured to receive data from a non-volatile memory and configured to receive data from a shadow memory, a shift register configured to generate a first signature from the data received from the non-volatile memory and configured to generate a second signature from the data received from the shadow memory; a signature storage configured to store the first signature; and a shadow memory checking controller configured to enable the multiplexor to send the data from the non-volatile memory to the shift register, and send a command to reload the shadow memory with data from the non-volatile memory in response to receiving an error flag. The IC also includes a comparator circuit configured to compare the first signature and the second signature and configured to send the error flag in response to the first signature and the second signature being different.