Patents by Inventor Lucas Martins Chaves

Lucas Martins Chaves has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Formal verification with EDA application and hardware prototyping platform
    Patent number: 11138357
    Abstract: A formal verification EDA application can be configured to receive a circuit design of an IC chip. The circuit design of the IC chip comprises a set of properties for the IC chip and constraints for the IC chip. The formal verification EDA application generates an array of CNF files based on the circuit design of the IC chip. Each CNF file can include a Boolean expression that characterizes a selected property of the set of properties and data fields characterizing initial states for literals in the Boolean expression and the constraints of the IC chip. The formal verification application can also be configured to output the array of CNF files to a hardware prototyping platform. The hardware prototyping platform can be configured to execute a hardware instantiated SAT solver for the Boolean expression in each CNF file in the array of CNF files.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: October 5, 2021
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Tulio Paschoalin Leao, Petros Daniel Fernandes de Medeiros Félix, Julia Pinheiro de Oliveira, Arthur Ribeiro Araujo, Lucas Martins Chaves, Andrei dos Santos Silva, Pablo Nunes Agra Belmonte
  • System, method, and computer program product for determining suitability for formal verification
    Patent number: 10956640
    Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using a processor, an electronic design and providing at least a portion of the electronic design to a machine learning engine. Embodiments may further include automatically determining, based upon, at least in part, an output of the machine learning engine whether or not the at least a portion of the electronic design is amenable to formal verification.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: March 23, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Georgia Penido Safe, Mirlaine Aparecida Crepalde, Yumi Monma, Felipe Althoff, Fernanda Augusta Braga, Lucas Martins Chaves, Pedro Bruno Neri Silva, Mariana Ferreira Marques, Vincent Gregory Reynolds