Abstract: Methods, systems, and devices for a dynamic parity scheme are described. A memory system may include a memory device with multiple blocks of memory cells, where each block includes a first quantity of pages of memory cells storing data and a second quantity of pages of memory cells storing parity information associated with the data. In some cases, the memory system may increase the quantity of pages in a block of memory cells storing parity information to improve a reliability of the data stored in the block of memory cells. For example, the memory system may increase the quantity of pages storing parity information at the block of memory cells after performing a threshold quantity of access operations at the block of memory cells or in response to detecting more than a threshold quantity of errors in data stored at the block of memory cells.

Abstract: Methods, systems, and devices are described to indicate, in an entry of logical to physical (L2P) mapping information stored at a host system, whether data associated with the entry is sequential to other data associated with a next entry or a previous entry. Each entry may have a third field, which may indicate whether the data is sequential. Based on the third field, the host system may determine whether data to be read from a memory system is sequential. The host system may transmit one read command to the memory system if the data is sequential, where the read command may include at least a portion of an L2P entry associated with the data. Similarly, based on the third field, the memory system may determine whether the data to be read is sequential, and may read additional, sequential data if the memory system determines that the data is sequential.

Abstract: Methods, systems, and devices for integrating a pivot table in a logical-to-physical mapping of a memory system are described. The memory system may receive a read command and read a first entry of a first subset of mapping and a second entry of a second subset of mapping. The second entry may include at least a portion of a pivot table associated with physical addresses of a non-volatile memory device. The memory system may retrieve data from a physical address identified in the pivot table, rather than access a different portion of the logical-to-physical mapping. The memory system may transmit, to a host system, the data retrieved from the physical address identified in the pivot table.

Abstract: Methods, systems, and devices for write booster buffer and hibernate are described. The memory system may initiate a first operation to enter a first power mode having a lower power consumption than a second power mode. In some cases, the memory system may determine whether a quantity of data stored in a buffer of single-level cells associated with write booster information satisfies a threshold based on initiating the first operation. The memory system may determine whether to perform a second operation to transfer the quantity of data stored in the buffer of single-level cells to a portion of memory comprising multiple level cells based on determining whether the quantity of data satisfies the threshold. The memory system may enter the first power mode based on determining to perform the second operation to transfer the quantity of data from the buffer to the portion of memory.

Abstract: Methods, systems, and devices for usage level identification for memory device addresses are described. Systems, techniques, and devices are described herein in which a memory device may determine where to store data according to a level of usage of the data. The memory device may receive a write command indicating data to be written, a type of the data, and a logical address of a memory array for writing the data. The memory device may identify an entry associated with the logical address in a table that maps the logical address to a physical address of the memory array. The entry may include a field configured to maintain a level of usage for the logical address. The memory device may update the level of usage value according to a process and write the data to a physical address of the memory array based on the level of usage value.

Abstract: Methods, systems, and devices for techniques for priority information are described. A memory system may be configured to receive, at a memory system, an indication that data is critical to operating the memory system; receive the data that is critical to operating the memory system based at least in part on the indication; select one more parameters to provide a reliability of a storage of the data into a memory device of the memory system based at least in part on receiving the indication and receiving the data; and program the data into the memory device of the memory system using the one or more parameters based at least in part on selecting the one or more parameters.

Abstract: Methods, systems, and devices for a dynamic parity scheme are described. A memory system may include a memory device with multiple blocks of memory cells, where each block includes a first quantity of pages of memory cells storing data and a second quantity of pages of memory cells storing parity information associated with the data. In some cases, the memory system may increase the quantity of pages in a block of memory cells storing parity information to improve a reliability of the data stored in the block of memory cells. For example, the memory system may increase the quantity of pages storing parity information at the block of memory cells after performing a threshold quantity of access operations at the block of memory cells or in response to detecting more than a threshold quantity of errors in data stored at the block of memory cells.

Abstract: Methods, systems, and devices for low-power boot-up for memory systems are described. A memory system may be configured to receive, over a first conductive path of a second communication interface, a first indication to boot-up a memory system and a first communication interface associated with the memory system, wherein the first communication interface includes a plurality of conductive paths; receive, over a second conductive path of the second communication interface, a second indication whether to perform a boot-up operation of the memory system using a low-power mode or a high-power mode based at least in part on receiving the first indication; and boot the memory system according to the low-power mode or the high-power mode based at least in part on receiving the second indication.

Abstract: Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.

Abstract: Methods, systems, and devices for automotive boot optimization are described. For instance, a memory system may record addresses that are accessed as part of multiple phases of a first boot-up procedure. During a second boot-up procedure, the memory system may transfer, from a logical block address of a non-volatile memory device to a volatile memory device, information for a respective phase based on the recording of the phases of the first boot-up procedure. The memory system may receive a command to transmit the information to a host system as part of the respective phase after transferring the information from the non-volatile device to the volatile memory device.

Abstract: A processing device of a memory sub-system can monitor a plurality of received commands to identify a forced unit access command. The processing device can identify a metadata area of the memory device based on the forced unit access command. The processing device can also perform an action responsive to identifying a subsequent forced unit access command to the metadata area.

Abstract: Methods, systems, and devices for suspend operation with data transfer to a host system are described. A host system may transmit a read command to a memory system operating in a first mode of operation (e.g., a standard mode associated with a nominal power consumption) indicating for the memory system to transition to a second mode of operation (e.g., a suspend mode associated with a decreased power consumption). Here, the memory system may transmit an image of the memory system stored in volatile memory to the host system and transition the memory system to the second mode. Additionally, the host system may transmit, to the memory system operating in the second mode, a write command including the image and indicating for the memory system to transition to the first mode. Here, the memory system may write the image to the volatile memory and transition to the first mode.

Abstract: Methods, systems, and devices for data defragmentation for a system boot procedure are described. The memory system may determine a write random index associated with a boot procedure. The write random index may indicate a relationship between a first quantity of sequential logical addresses accessed as part of the boot procedure and a second quantity of random logical addresses accessed as part of the boot procedure. The memory system may determine whether the write random index satisfies a threshold based on determining the write random index. In some cases, the memory system may transfer, to a second portion of the memory system, data stored in a first portion of the memory system based on determining that the write random index satisfies the threshold. The memory system may receive a request to perform the boot procedure after transferring the data and output, to the host system, the data transferred.

Abstract: Described are systems and methods for prioritization of background media management operations in memory systems. An example system comprises a controller coupled to a memory array comprising a plurality of memory cells. The controller is configured to perform operations, comprising: identifying a plurality of address ranges referencing respective sets of memory cells of the memory array, wherein each address range is associated with a respective memory access operation counter reflecting a number of memory access operations that have been performed with respect to a corresponding set of memory cells; identifying, among the plurality of address ranges, an address range associated with a maximum value of a corresponding memory access operation counter; and causing a media management operation to be performed with respect to a set of memory cells referenced by the identified address range.

Abstract: The present disclosure includes apparatuses and methods related to a hybrid memory system interface. An example computing system includes a processing resource and a storage system coupled to the processing resource via a hybrid interface. The hybrid interface can provide an input/output (I/O) access path to the storage system that supports both block level storage I/O access requests and sub-block level storage I/O access requests.

Abstract: Methods, systems, and devices for techniques for detection of shutdown patterns are described. A memory device may receive a set of commands from a host device. The memory device may determine whether the set of commands are associated with a shutdown procedure based on a pattern of the received set of commands. The memory device may initiate one or more operations associated with the shutdown procedure based on identifying that the set of commands are associated with the shutdown procedure. The memory device may receive a shutdown command for the shutdown procedure after initiating the one or more operations associated with the shutdown procedure. The memory device may determine that the set of commands are associated with the shutdown procedure based on a quantity of the set of commands, one or more types of the set of commands, other thresholds associated with the pattern, or a combination thereof.

Abstract: A processing device of a memory sub-system can monitor a plurality of received commands to identify a forced unit access command. The processing device can identify a metadata area of the memory device based on the forced unit access command. The processing device can also perform an action responsive to identifying a subsequent forced unit access command to the metadata area.

Abstract: Methods, systems, and devices for commanded device states for a memory system are described. For example, a memory system may be configured with different device states that are each associated with a respective allocation of resources (e.g., feature sets) for operations of the memory system. Resource allocations corresponding to the different device states may be associated with different combinations of memory management configurations, error control configurations, trim parameters, degrees of parallelism, or endurance configurations, among other parameters of the memory system, which may support different tradeoffs between performance characteristics of the memory system. A host system may be configured to evaluate various parameters of operating the host system, and to transmit commands for a memory system to enter a desired device state of the memory system.

Abstract: Methods, systems, and devices for data defragmentation control are described. A memory system may include one or more regions of logical addresses and a plurality of memory cells arranged according to a plurality of physical addresses. In some instances, data may be stored to one or more discontinuous physical addresses and it may be desirable rearrange the data to be within continuous physical addresses (e.g., it may be desirable to defragment the data). Accordingly, the data stored to the one or more discontinuous physical addresses may be arranged (e.g., rearranged) to be within continuous physical addresses based at least in part on a value stored to one or more registers of the memory system.

Abstract: Methods, systems, and devices for detecting page fault traffic are described. A memory device may execute a self-learning algorithm to determine a priority size for read requests, such as a maximum readahead window size or other size related to page faults in a memory system. The memory device may determine the priority size based at least in part on by tracking how many read requests are received for different sizes of sets of data. Once the priority size is determined, the memory device may detect subsequent read requests for sets of data having the priority size, and the memory device may prioritize or other optimize the execution of such read requests.