Abstract: Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.

Abstract: An aspect includes a method for auto-disabling dynamic random access memory (DRAM) error checking based on a threshold. A method includes receiving data at a DRAM and executing error checking logic based on the data. The error checking logic detects an error condition in the data and it is determined, at the DRAM, whether detecting the error condition in the data causes an error threshold to be reached. The error checking logic is disabled at the DRAM in response to determining that detecting the error condition in the data causes the error the error threshold to be reached.

Abstract: An NVDIMM requests an authentication object in response to a detected command to initiate a save operation to copy first memory data located in volatile memory on the NVDIMM to non-volatile memory located on the NVDIMM. The NVDIMM determines based on the authentication object that authentication has failed. The NVDIMM implements, in response to determining that authentication has failed, a security measure to prevent recovery of the first memory data.

Abstract: Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.

Abstract: Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.

Abstract: An NVDIMM requests an authentication object in response to a detected command to initiate a save operation to copy first memory data located in volatile memory on the NVDIMM to non-volatile memory located on the NVDIMM. The NVDIMM determines based on the authentication object that authentication has failed. The NVDIMM implements, in response to determining that authentication has failed, a security measure to prevent recovery of the first memory data.

Abstract: An NVDIMM requests an authentication object in response to a detected command to initiate a save operation to copy first memory data located in volatile memory on the NVDIMM to non-volatile memory located on the NVDIMM. The NVDIMM determines based on the authentication object that authentication has failed. The NVDIMM implements, in response to determining that authentication has failed, a security measure to prevent recovery of the first memory data.

Abstract: Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.

Abstract: Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.

Abstract: Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.

Abstract: A method, system, and/or computer program product corrects a data error that has been caused by a break in a conductor link in a memory. A memory controller detects a line malfunction in a data bit transmission line between a first bit node and a second bit node in a memory, and then identifies a constant voltage state at the second bit node that is caused by the line malfunction. In response to determining that the constant voltage state is non-representative of the bit value intended to be transmitted from the first bit node to the second bit node, an inversion logic inverts bit values for all bits in an original bit array to create an inverted bit array, which is stored in the array of memory cells for future retrieval and re-inversion, in order to reconstruct the original bit array.

Abstract: An aspect includes a method for auto-disabling dynamic random access memory (DRAM) error checking based on a threshold. A method includes receiving data at a DRAM and executing error checking logic based on the data. The error checking logic detects and error condition in the data and it is determined, at the DRAM, whether detecting the error condition in the data causes an error threshold to be reached. The error checking logic is disabled at the DRAM in response to determining that detecting the error condition in the data causes the error the error threshold to be reached.

Abstract: An aspect includes a method for auto-disabling dynamic random access memory (DRAM) error checking based on a threshold. A method includes receiving data at a DRAM from a memory controller and executing error checking logic based on the data. The error checking logic detects an error condition in the data and it is determined, at the DRAM, whether detecting the error condition in the data causes an error threshold to be reached. The error checking logic is disabled at the DRAM in response to determining that detecting the error condition in the data causes the error the error threshold to be reached. The error condition is communicated to the memory controller in response to determining that detecting the error condition does not cause the error threshold to be reached.

Abstract: An aspect includes a method for auto-disabling dynamic random access memory (DRAM) error checking based on a threshold. A method includes receiving data at a DRAM from a memory controller and executing error checking logic based on the data. The error checking logic detects and error condition in the data and it is determined, at the DRAM, whether detecting the error condition in the data causes an error threshold to be reached. The error checking logic is disabled at the DRAM in response to determining that detecting the error condition in the data causes the error the error threshold to be reached. The error condition is communicated to the memory controller in response to determining that detecting the error condition does not cause the error threshold to be reached.

Abstract: A method, system, and/or computer program product corrects a data error that has been caused by a break in a conductor link in a memory. A memory controller detects a line malfunction in a data bit transmission line between a first bit node and a second bit node in a memory, and then identifies a constant voltage state at the second bit node that is caused by the line malfunction. In response to determining that the constant voltage state is non-representative of the bit value intended to be transmitted from the first bit node to the second bit node, an inversion logic inverts bit values for all bits in an original bit array to create an inverted bit array, which is stored in the array of memory cells for future retrieval and re-inversion, in order to reconstruct the original bit array.

Abstract: An aspect includes viewing contents of a command queue that contains commands waiting to be sent in a specified order to a memory for execution at the memory. Command pattern data that includes patterns of commands and associated estimated power consumptions is accessed. The contents of the command queue are searched for the patterns of commands. One of the patterns of commands is located in the contents of the command queue. A suggested power management action is determined for the memory based on the located pattern of commands and its associated estimated power consumption. The suggested power management action is sent to a power control engine of the memory prior to a first command in the located pattern of commands being sent to the memory for execution.