Abstract: A semiconductor device including a housing, a semiconductor chip disposed within the housing and having first and second metal electrodes, a first lead frame having a first end extending out of the housing and a second end terminating in a die pad, a top surface of the die pad including a cavity having a first quantity of solder disposed therein for electrically connecting the die pad to the first metal electrode, a second lead frame having a first end extending out of the housing and having a second end disposed adjacent the semiconductor chip, and a clip having a first end connected to the second of the lead frame and a second end extending over the semiconductor chip, a bottom surface of the second end of the clip including a recess having a second quantity of solder disposed therein for electrically connecting the clip to the second metal electrode.

Abstract: A discrete semiconductor packaging structure and associated methods thereof. The structure includes a housing, a chip assembly pad being encapsulated by the housing, where the chip assembly pad is configured for coupling to a semiconductor chip. The structure further includes one or more leads, at least partially encapsulated by the housing, a clip including one or more terminals and a chip linker, where the terminals being configured for coupling to one or more leads, and a heat dissipation block, where the chip linker being coupled between the semiconductor chip and the heat dissipation block. The heat dissipation block is configured for removing heat from the semiconductor chip during operation.

Abstract: A surface mounting apparatus, structure, and associated methods thereof. The surface mounting apparatus includes a housing, a lead frame, at least partially encapsulated by the housing. The lead frame includes a chip mounting surface having a chip mounting pad, and one or more first stress relief features disposed outside of the chip mounting surface. The apparatus further includes another lead frame, at least partially encapsulated by the housing.

Abstract: An overvoltage protection device may include an n-type semiconductor substrate, a p-type layer disposed atop the n-type semiconductor substrate, and a passivation region formed in the n-type semiconductor substrate and the p-type layer, wherein the passivation region comprises a semi-insulating polycrystalline silicon (SIPOS) layer.

Abstract: Provided herein are package structures including a first lead frame having a first pedestal and a first lead extending from the first pedestal. A first perimeter ridge defines a first recessed area in a first main side of the first pedestal, wherein a die pad is positioned within the first recessed area. The package structure may further include a chip layer having a first main side opposite a second main side, wherein the second main side is in abutment with the first perimeter ridge of the pedestal of the first lead frame. The package structure may further include a clip including a second pedestal and a lead connector extending from the second pedestal, wherein a second perimeter ridge defines a second recessed area in a second main side of the second pedestal, and wherein the second perimeter ridge is in abutment with the first main side of the chip layer.

Abstract: A discrete semiconductor package includes a semiconductor device, a left lead, and a right lead. The semiconductor device has a first side and a second side, the second side being opposite the first side. The left lead has a left terminal and a platform to support the semiconductor device on the first side. The right lead has a right terminal and a clip coin to support the semiconductor device on the second side.

Abstract: A discrete power semiconductor package includes a semiconductor chip, a heatsink, a first lead, a second lead, and a clip. The heatsink is adjacent the semiconductor chip and draws heat away from the semiconductor chip. The clip binds the semiconductor chip to the heatsink and includes a chip linker, a first terminal, and a second terminal. The chip linker is atop the semiconductor chip. The first terminal connects to the first lead and the second terminal connects to the second lead.