Abstract: Some embodiments include an integrated assembly having first and second source/drain regions laterally offset from one another. Metal silicide is adjacent to lateral surfaces of the source/drain regions. Metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source/drain regions through the metal silicide and the metal. Capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes, A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.

Abstract: A semiconductor device including a housing, a semiconductor chip disposed within the housing and having first and second metal electrodes, a first lead frame having a first end extending out of the housing and a second end terminating in a die pad, a top surface of the die pad including a cavity having a first quantity of solder disposed therein for electrically connecting the die pad to the first metal electrode, a second lead frame having a first end extending out of the housing and having a second end disposed adjacent the semiconductor chip, and a clip having a first end connected to the second of the lead frame and a second end extending over the semiconductor chip, a bottom surface of the second end of the clip including a recess having a second quantity of solder disposed therein for electrically connecting the clip to the second metal electrode.

Abstract: The present application provides immune cells (such as T cells) comprising a chimeric antibody-T cell receptor (TCR) construct (caTCR) and a chimeric signaling receptor (CSR) construct. The caTCR comprises an antigen-binding module that specifically binds to a target antigen and a T cell receptor module (TCRM) capable of recruiting at least one TCR-associated signaling molecule, and the CSR comprises a ligand-binding domain that specifically binds to a target ligand and a co-stimulatory signaling domain capable of providing a stimulatory signal to the immune cell. Also provided are methods of making and using these cells.

Abstract: The techniques disclosed herein enable systems to translate three-dimensional experiences into user accessible experiences to improve accessibility for users with disabilities. Namely, the discussed system enables users with disabilities to create and personalize objects for use in the three-dimensional experience. This is accomplished by translating and grouping components from a three-dimensional space to form an intuitive and logical hierarchy. The grouped components are then organized into an accessible user interface which a user with disabilities can navigate using simplified inputs and assistive technologies. In this way, users with disabilities can be empowered to personalize their user experience and understand a three-dimensional space in a layered, well-defined format.

Abstract: A discrete semiconductor packaging structure and associated methods thereof. The structure includes a housing, a chip assembly pad being encapsulated by the housing, where the chip assembly pad is configured for coupling to a semiconductor chip. The structure further includes one or more leads, at least partially encapsulated by the housing, a clip including one or more terminals and a chip linker, where the terminals being configured for coupling to one or more leads, and a heat dissipation block, where the chip linker being coupled between the semiconductor chip and the heat dissipation block. The heat dissipation block is configured for removing heat from the semiconductor chip during operation.

Abstract: A surface mounting apparatus, structure, and associated methods thereof. The surface mounting apparatus includes a housing, a lead frame, at least partially encapsulated by the housing. The lead frame includes a chip mounting surface having a chip mounting pad, and one or more first stress relief features disposed outside of the chip mounting surface. The apparatus further includes another lead frame, at least partially encapsulated by the housing.

Abstract: A computer implemented method for certifying robustness of image classification in a neural network is provided. The method includes initializing a neural network model. The neural network model includes a problem space and a decision boundary. A processor receives a data set of images, image labels, and a perturbation schedule. Images are drawn from the data set in the problem space. A distance from the decision boundary is determined for the images in the problem space. A re-weighting value is applied to the images. A modified perturbation magnitude is applied to the images. A total loss function for the images in the problem space is determined using the re-weighting value. A confidence level of the classification of the images in the data set is evaluated for certifiable robustness.

Abstract: Features described herein generally relate to learning and recognizing object-centered routines. Particularly, object-centered routines can be learned and recognized by collecting data corresponding to a user. The data can include information representing interactions by the user with respect to objects in an environment. The routine can be learned by presenting a visual graph to the user. The user can define nodes associating an interaction with an object, specify a relationship between nodes, and arrange the nodes into segments. The visual graph can be stored, and a routine can be recognized based on the visual graph.

Abstract: Some embodiments include an integrated assembly having first and second source/drain regions laterally offset from one another. Metal silicide is adjacent to lateral surfaces of the source/drain regions. Metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source/drain regions through the metal silicide and the metal. Capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes, A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.

Abstract: A converter includes a DC bus, a first DC-DC converter, a second DC-DC converter, and a plurality of circulating current suppression circuits. The first DC-DC converter is coupled to the DC bus and includes a first plurality of switches. The second DC-DC converter is coupled to the DC bus in parallel with the first DC-DC converter. The second DC-DC converter includes a second plurality of switches. The plurality of circulating current suppression circuits are coupled to the DC bus and are further respectively coupled to the first DC-DC converter and the second DC-DC converter. Each of the plurality of circulating current suppression circuits has a resonant frequency at or around a switching frequency for the first and second pluralities of switches. The plurality of circulating current suppression circuits is configured to suppress current at or around the switching frequency and pass at least direct current.

Abstract: An overvoltage protection device may include an n-type semiconductor substrate, a p-type layer disposed atop the n-type semiconductor substrate, and a passivation region formed in the n-type semiconductor substrate and the p-type layer, wherein the passivation region comprises a semi-insulating polycrystalline silicon (SIPOS) layer.

Abstract: Provided herein are package structures including a first lead frame having a first pedestal and a first lead extending from the first pedestal. A first perimeter ridge defines a first recessed area in a first main side of the first pedestal, wherein a die pad is positioned within the first recessed area. The package structure may further include a chip layer having a first main side opposite a second main side, wherein the second main side is in abutment with the first perimeter ridge of the pedestal of the first lead frame. The package structure may further include a clip including a second pedestal and a lead connector extending from the second pedestal, wherein a second perimeter ridge defines a second recessed area in a second main side of the second pedestal, and wherein the second perimeter ridge is in abutment with the first main side of the chip layer.

Abstract: A discrete semiconductor package includes a semiconductor device, a left lead, and a right lead. The semiconductor device has a first side and a second side, the second side being opposite the first side. The left lead has a left terminal and a platform to support the semiconductor device on the first side. The right lead has a right terminal and a clip coin to support the semiconductor device on the second side.

Abstract: A discrete power semiconductor package includes a semiconductor chip, a heatsink, a first lead, a second lead, and a clip. The heatsink is adjacent the semiconductor chip and draws heat away from the semiconductor chip. The clip binds the semiconductor chip to the heatsink and includes a chip linker, a first terminal, and a second terminal. The chip linker is atop the semiconductor chip. The first terminal connects to the first lead and the second terminal connects to the second lead.