Abstract: An integrated circuit includes a plurality of power transistor driver channels for driving external loads. The driver channels can be selectively configured as high side or low side driver channels. The integrated circuit includes, for each driver channel, a respective analog test circuit and a respective controller. The integrated circuit includes a single counter connected to each of the controllers for simultaneously controlling off-state diagnosis timing windows for the driver channels.

Abstract: A communication system has a galvanic isolation link coupling a first circuit to a second circuit. The first circuit transmits first data signals to the second circuit and receives second data signals from the second circuit in response to the first data signals. The data signals are transmitted in consecutive time slots of a determined time duration via the galvanic isolation link. The first data signals include polling signals transmitted from the first circuit to the second circuit during consecutive time slots, and on-demand access requests transmitted from the first circuit to the second circuit. The second data signals include status response signals transmitted from the second circuit to the first circuit in response to polling signals received from the first circuit, and access response signals transmitted from the second circuit to the first circuit in response to access requests received from the first circuit.

Abstract: A communication system has a galvanic isolation link coupling a first circuit to a second circuit. The first circuit transmits first data signals to the second circuit and receives second data signals from the second circuit in response to the first data signals. The data signals are transmitted in consecutive time slots of a determined time duration via the galvanic isolation link. The first data signals include polling signals transmitted from the first circuit to the second circuit during consecutive time slots, and on-demand access requests transmitted from the first circuit to the second circuit. The second data signals include status response signals transmitted from the second circuit to the first circuit in response to polling signals received from the first circuit, and access response signals transmitted from the second circuit to the first circuit in response to access requests received from the first circuit.