Patents by Inventor Lucian Codrescu

Lucian Codrescu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190196867
    Abstract: A processor includes priority adjustment circuitry configured to adjust a priority of a thread of multiple threads configured to execute tasks to have a software-defined priority value or a designated high priority value. The processor also includes circuitry configured to identify a lowest priority thread of the multiple threads and a control unit configured to cause the lowest priority thread to take a pending interrupt.
    Type: Application
    Filed: May 18, 2018
    Publication date: June 27, 2019
    Inventors: Erich Plondke, Suresh Kumar Venkumahanti, Lin Wang, Lucian Codrescu
  • Patent number: 10289412
    Abstract: Systems and methods for generating a floating point constant value from an instruction are disclosed. A first field of the instruction is decoded as a sign bit of the floating point constant value. A second field of the instruction is decoded to correspond to an exponent value of the floating point constant value. A third field of the instruction is decoded to correspond to the significand of the floating point constant value. The first field, the second field, and the third field are combined to form the floating point constant value. The exponent value may include a bias, and a bias constant may be added to the exponent value to compensate for the bias. The third field may comprise the most significant bits of the significand. Optionally, the second field and the third field may be shifted by first and second shift values respectively before they are combined to form the floating point constant value.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: May 14, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Erich James Plondke, Lucian Codrescu, Charles Joseph Tabony, Swaminathan Balasubramanian
  • Patent number: 10133598
    Abstract: An apparatus includes a processor and a guest operating system. In response to receiving a request to create a task, the guest operating system requests a hypervisor to create a virtual processor to execute the requested task. The virtual processor is schedulable on the processor.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: November 20, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Erich James Plondke, Lucian Codrescu
  • Patent number: 10120692
    Abstract: A method of compressing a sequence of program instructions begins by examining a program instruction stream to identify a sequence of two or more instructions that meet a parameter. The identified sequence of two or more instructions is replaced by a selected type of layout instruction which is then compressed. A method of decompressing accesses an X-index and a Y-index together as a compressed value. The compressed value is decompressed to a selected type of layout instruction which is decoded and replaced with a sequence of two or more instructions. An apparatus for decompressing includes a storage subsystem configured for storing compressed instructions, wherein a compressed instruction comprises an X-index and a Y-index. A decompressor is configured for translating an X-index and Y-index accessed from the storage subsystem to a selected type of layout instruction which is decoded and replaced with a sequence of two or more instructions.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: November 6, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Sergei Larin, Lucian Codrescu, Anshuman Das Gupta
  • Patent number: 10114756
    Abstract: A method includes reading, by a processor, one or more configuration values from a storage device or a memory management unit. The method also includes loading the one or more configuration values into one or more registers of the processor. The one or more registers are useable by the processor to perform address translation.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 30, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Christopher Edward Koob, Erich James Plondke, Piyush Patel, Thomas Andrew Sartorius, Lucian Codrescu
  • Patent number: 10055227
    Abstract: Systems and methods for tracking and switching between execution modes in processing systems. A processing system is configured to execute instructions in at least two instruction execution triodes including a first and second execution mode chosen from a classic/aligned mode and a compressed/unaligned mode. Target addresses of selected instructions such as calls and returns are forcibly misaligned in the compressed mode, such one or more bits, such as, the least significant bits (alignment bits) of the target address in the compressed mode are different from the corresponding alignment bits in the classic mode. When the selected instructions are encountered during execution in the first mode, a decision to switch operation to the second mode is based on analyzing the alignment bits of the target address of the selected instruction.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: August 21, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Charles Joseph Tabony, Erich James Plondke, Lucian Codrescu, Suresh K. Venkumahanti, Evandro Carlos Menezes
  • Patent number: 10025711
    Abstract: Embodiments disclosed in the detailed description include hybrid write-through/write-back cache policy managers, and related systems and methods. A cache write policy manager is configured to determine whether at least two caches among a plurality of parallel caches are active. If all of one or more other caches are not active, the cache write policy manager is configured to instruct an active cache among the parallel caches to apply a write-hack cache policy. In this manner, the cache write policy manager may conserve power and/or increase performance of a singly active processor core. If any of the one or more other caches are active, the cache write policy manager is configured to instruct an active cache among the parallel caches to apply a write-through cache policy. In this manner, the cache write policy manager facilitates data coherency among the parallel caches when multiple processor cores are active.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: July 17, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Peter G. Sassone, Christopher Edward Koob, Dana M. Vantrease, Suresh K. Venkumahanti, Lucian Codrescu
  • Patent number: 9952866
    Abstract: A method of compressing a sequence of program instructions begins by examining a program instruction stream to identify a sequence of two or more instructions that meet a parameter. The identified sequence of two or more instructions is replaced by a selected type of layout instruction which is then compressed. A method of decompressing accesses an X-index and a Y-index together as a compressed value. The compressed value is decompressed to a selected type of layout instruction which is decoded and replaced with a sequence of two or more instructions. An apparatus for decompressing includes a storage subsystem configured for storing compressed instructions, wherein a compressed instruction comprises an X-index and a Y-index. A decompressor is configured for translating an X-index and Y-index accessed from the storage subsystem to a selected type of layout instruction which is decoded and replaced with a sequence of two or more instructions.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: April 24, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Sergei Larin, Lucian Codrescu, Anshuman Das Gupta
  • Publication number: 20180081687
    Abstract: A method of determining an execution order of memory operations performed by a processor includes executing at least one single-instruction, multiple-data (SIMD) scatter operation by the processor to store data to a memory. The method further includes executing one or more instructions by the processor to determine the execution order of a set of memory operations. The set of memory operations includes the at least one SIMD scatter operation.
    Type: Application
    Filed: September 22, 2016
    Publication date: March 22, 2018
    Inventors: Eric Mahurin, Lucian Codrescu
  • Publication number: 20170371657
    Abstract: Systems and methods relate to efficient memory operations. A single instruction multiple data (SIMD) gather operation is implemented with a gather result buffer located within or in close proximity to memory, to receive or gather multiple data elements from multiple orthogonal locations in a memory, and once the gather result buffer is complete, the gathered data is transferred to a processor register. A SIMD copy operation is performed by executing two or more instructions for copying multiple data elements from multiple orthogonal source addresses to corresponding multiple destination addresses within the memory, without an intermediate copy to a processor register. Thus, the memory operations are performed in a background mode without direction by the processor.
    Type: Application
    Filed: June 24, 2016
    Publication date: December 28, 2017
    Inventors: Eric Wayne MAHURIN, Jakub Pawal GOLAB, Lucian CODRESCU
  • Patent number: 9823928
    Abstract: An instruction identifies a register and a memory location. Upon execution of the instruction by a processor, an item is loaded from the memory location and a shift and insert operation is performed to shift data in the register and to insert the item into the register.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: November 21, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Mao Zeng, Lucian Codrescu, Erich James Plondke, Ajay Anant Ingle
  • Patent number: 9824013
    Abstract: Systems and methods for allocation of cache lines in a shared partitioned cache of a multi-threaded processor. A memory management unit is configured to determine attributes associated with an address for a cache entry associated with a processing thread to be allocated in the cache. A configuration register is configured to store cache allocation information based on the determined attributes. A partitioning register is configured to store partitioning information for partitioning the cache into two or more portions. The cache entry is allocated into one of the portions of the cache based on the configuration register and the partitioning register.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: November 21, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Christopher Edward Koob, Ajay Anant Ingle, Lucian Codrescu, Suresh K. Venkumahanti
  • Patent number: 9785434
    Abstract: An apparatus, system and method of determining an extremum are disclosed. A reference location identifier and a reference extremum are coupled. An input extremum of an input data set is determined and a corresponding location identifier of the input extremum is also determined. The input extremum is compared with the reference extremum to determine an output extremum and output location identifier, based on the comparison.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 10, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Erich J. Plondke, Lucian Codrescu, Mao Zeng, Swaminathan Balasubramanian, David J. Hoyle
  • Patent number: 9715392
    Abstract: A method includes identifying, at a scheduling unit, a resource conflict at a shared processing resource that is accessible by a first processing cluster and by a second processing cluster, where the first processing cluster, the second processing cluster, and the shared processing resource are included in a very long instruction word (VLIW) processing unit. The method also includes resolving the resource conflict.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: July 25, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Suresh Kumar Venkumahanti, Ankit Ghiya, Peter Gene Sassone, Lucian Codrescu, Suman Mamidi
  • Patent number: 9678758
    Abstract: Systems and methods for implementing certain load instructions, such as vector load instructions by cooperation of a main processor and a coprocessor. The load instructions which are identified by the main processor for offloading to the coprocessor are committed in the main processor without receiving corresponding load data. Post-commit, the load instructions are processed in the coprocessor, such that latencies incurred in fetching the load data are hidden from the main processor. By implementing an out-of-order load data buffer associated with an in-order instruction buffer, the coprocessor is also configured to avoid stalls due to long latencies which may be involved in fetching the load data from levels of memory hierarchy, such as L2, L3, L4 caches, main memory, etc.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: June 13, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Lucian Codrescu, Christopher Edward Koob, Eric Wayne Mahurin, Suresh Kumar Venkumahanti
  • Patent number: 9678754
    Abstract: A system and method of processing a hierarchical very long instruction word (VLIW) packet is disclosed. In a particular embodiment, a method of processing instructions is disclosed. The method includes receiving a hierarchical VLIW packet of instructions and decoding an instruction from the packet to determine whether the instruction is a single instruction or whether the instruction includes a subpacket that includes a plurality of sub-instructions. The method also includes, in response to determining that the instruction includes the subpacket, executing each of the sub-instructions.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: June 13, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Lucian Codrescu, Erich James Plondke, Ajay Anant Ingle, Suresh K. Venkumahanti, Charles Joseph Tabony
  • Patent number: 9632781
    Abstract: Techniques are provided for executing a vector alignment instruction. A scalar register file in a first processor is configured to share one or more register values with a second processor, the one or more register values accessed from the scalar register file according to an Rt address specified in a vector alignment instruction, wherein a start location is determined from one of the shared register values. An alignment circuit in the second processor is configured to align data identified between the start location within a beginning Vu register of a vector register file (VRF) and an end location of a last Vu register of the VRF according to the vector alignment instruction. A store circuit is configured to select the aligned data from the alignment circuit and store the aligned data in the vector register file according to an alignment store address specified by the vector alignment instruction.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: April 25, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Ajay A. Ingle, Marc M. Hoffman, Jose Fridman, Lucian Codrescu
  • Patent number: 9626579
    Abstract: A method includes receiving image data and performing a non-maximum suppression (NMS) operation on the image data. The method also includes initiating an edge tracking by hysteresis (ETH) operation on a portion of the image data prior to completion of the NMS operation.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: April 18, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Kim-Chyan Gan, Mao Zeng, Lucian Codrescu
  • Patent number: 9606818
    Abstract: An apparatus includes a primary hypervisor that is executable on a first set of processors and a secondary hypervisor that is executable on a second set of processors. The primary hypervisor may define settings of a resource and the secondary hypervisor may use the resource based on the settings defined by the primary hypervisor. For example, the primary hypervisor may program memory address translation mappings for the secondary hypervisor. The primary hypervisor and the secondary hypervisor may include their own schedulers.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 28, 2017
    Assignee: Qualcomm Incorporated
    Inventors: Erich James Plondke, Lucian Codrescu, Christopher Edward Koob, Piyush Patel, Thomas Andrew Sartorius
  • Publication number: 20170046156
    Abstract: Systems and methods pertain to looking up entries of a table. A processor receives one or more single instruction multiple data (SIMD) instructions, including a first SIMD instruction which specifies a first subset of indices. A first subset of table entries is looked up, using a crossbar, with the first subset of indices. A first vector output of the first SIMD instruction is based on whether the outputs of the crossbar belong to a desired subset of table entries. Similarly, second, third, and fourth SIMD instructions specify corresponding second, third, and fourth subsets of indices to lookup the remaining table entries using the crossbar. The size of the crossbar is based on the number of indices in the subset of indices used to lookup table entries.
    Type: Application
    Filed: August 14, 2015
    Publication date: February 16, 2017
    Inventors: Eric Wayne MAHURIN, Lucian CODRESCU, Erich James PLONDKE, David HOYLE, Mao ZENG, Kim-Chyan GAN