Abstract: A method and system provide processing instructions in a multi-threaded process including the use of breakpoint instructions for generating debugging event(s). A debugging event is generated in response to the execution of breakpoint instructions and executes debugging instructions in response to the debugging event. The debugging instructions debug processing instructions in the multi-threaded processor by transitioning at least one or more threads into a debugging mode. A debugging return is generated for reporting the executing debugging instructions in the subset of the threads of the multi-threaded processor.

Abstract: A method of compressing a sequence of program instructions begins by examining a program instruction stream to identify a sequence of two or more instructions that meet a parameter. The identified sequence of two or more instructions is replaced by a selected type of layout instruction which is then compressed. A method of decompressing accesses an X-index and a Y-index together as a compressed value. The compressed value is decompressed to a selected type of layout instruction which is decoded and replaced with a sequence of two or more instructions. An apparatus for decompressing includes a storage subsystem configured for storing compressed instructions, wherein a compressed instruction comprises an X-index and a Y-index. A decompressor is configured for translating an X-index and Y-index accessed from the storage subsystem to a selected type of layout instruction which is decoded and replaced with a sequence of two or more instructions.

Abstract: An apparatus includes a memory that stores an instruction including an opcode and an operand. The operand specifies an immediate value or a register indicator of a register storing the immediate value. The immediate value is usable to identify a function call address. The function call address is selectable from a plurality of function call addresses.

Abstract: A system and method to access data from a portion of a level two memory or from a level one memory is disclosed. In a particular embodiment, the system includes a level one cache and a level two memory. A first portion of the level two memory is coupled to an input port and is addressable in parallel with the level one cache.

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. The method and system improve software instruction debugging operations by capturing real-time information relating to software execution flow and include and instructions and circuitry for operating a core processor process within a core processor. A non-intrusive debugging process operates within a debugging mechanism of a digital signal processor. Non-intrusively monitoring in real time predetermined aspects of software execution occurs with the core processing process and occurs in real-time on the processor. An embedded trace macrocell records selectable aspects of the non-intrusively monitored software execution and generates at least one breakpoint in response to events arising within the selectable aspects of the non-intrusively monitored software execution.

Abstract: Systems and method for configuring a page-based memory device without pre-existing dedicated metadata. The method includes reading metadata from a metadata portion of a page of the memory device, and determining a characteristic of the page based on the metadata. The memory device may be configured as a cache. The metadata may include address tags, such that determining the characteristic may include determining if desired information is present in the page, and reading the desired information if it is determined to be present in the page. The metadata may also include error-correcting code (ECC), such that determining the characteristic may include detecting errors present in data stored in the page. The metadata may further include directory information, memory coherency information, or dirty/valid/lock information.

Abstract: Programs often require constants that cannot be encoded in a native instruction format, such as 32-bits. To provide an extended constant, an instruction packet is formed with constant extender information and a target instruction. The constant extender information encoded as a constant extender instruction provides a first set of constant bits, such as 26-bits for example, and the target instruction provides a second set of constant bits, such as 6-bits. The first set of constant bits are combined with the second set of constant bits to generate an extended constant for execution of the target instruction. The extended constant may be used as an extended source operand, an extended address for memory access instructions, an extended address for branch type of instructions, and the like. Multiple constant extender instructions may be used together to provide larger constants than can be provided by a single extension instruction.

Abstract: Programs often require constants that cannot be encoded in a native instruction format, such as 32-bits. To provide an extended constant, an instruction packet is formed with constant extender information and a target instruction. The constant extender information encoded as a constant extender instruction provides a first set of constant bits, such as 26-bits for example, and the target instruction provides a second set of constant bits, such as 6-bits. The first set of constant bits are combined with the second set of constant bits to generate an extended constant for execution of the target instruction. The extended constant may be used as an extended source operand, an extended address for memory access instructions, an extended address for branch type of instructions, and the like. Multiple constant extender instructions may be used together to provide larger constants than can be provided by a single extension instruction.

Abstract: A system for translating compressed instructions to instructions in an executable format is described. A translation unit is configured to decompress compressed instructions into a native instruction format using X and Y indices accessed from a memory, a translation memory, and a program specified mix mask. A level 1 cache is configured to store the native instruction format for each compressed instruction. The memory may be configured as a paged instruction cache to store pages of compressed instructions intermixed with pages of uncompressed instructions. Methods of determining a mix mask for efficiently translating compressed instructions is also described. A genetic method uses pairs of mix masks as genes from a seed population of mix masks that are bred and may be mutated to produce pairs of offspring mix masks to update the seed population. A mix mask for efficiently translating compressed instructions is determined from the updated seed population.

Abstract: A method includes receiving an address at a tag state array of a cache. The cache is configurable to have a first size or a second size that is larger than the first size. The method includes identifying a first portion of the address as a set index and using the set index to locate at least one tag field of the tag state array. The method also includes identifying a second portion of the address to compare to a value stored at the at least one tag field and locating at least one state field of the tag state array associated with a particular tag field that matches the second portion. The method further includes identifying a cache line based on a comparison of a third portion of the address to at least two status bits of the at least one state field and retrieving the cache line.

Abstract: A Viterbi pack instruction is disclosed that masks the contents of a first predicate register with a first masking value and masks the contents of a second predicate register with a second masking value. The resulting masked data is written to a destination register. The Viterbi pack instruction may be implemented in hardware, firmware, software, or any combination thereof.

Abstract: Method and apparatus for performing two independent sum-of-absolute-difference (SAD) operations when receiving a single instruction (505, 705) is provided. The two operations may be performed in parallel. The operations process values stored in two source registers (405, 410) and the results are stored to a destination register (425). The source and destination registers each have two independently accessible sections, whereby a first SAD operation (401) can access a first section while a second independent SAD operation (402) can simultaneously access a second section of the register. The first SAD operation is performed on values in a first section of the source registers, the result being stored to a first section of the destination register. The second SAD operation is performed on values in a second section of the source registers, the result being stored to a second section of the destination register. The values may comprise pixel values.

Abstract: A system and method to execute a linear feedback-shift instruction is disclosed. In a particular embodiment the method includes executing an instruction at a processor by receiving source data and executing a bitwise logical operation on the source data and on reference data to generate intermediate data. The method further includes determining a parity value of the intermediate data, shifting the source data, and entering the parity value of the intermediate data into a data field of the shifted source data to produce resultant data.

Abstract: In a particular embodiment, a cache is disclosed that includes a tag state array that includes a tag area addressable by a set index. The tag state array also includes a state area addressable by a state address, where the set index and the state address include at least one common bit.

Abstract: A system and method for selective preclusion of bus access requests are disclosed. In an embodiment, a method includes determining a bus unit access setting at a logic circuit of a processor. The method also includes selectively precluding a bus unit access request based on the bus unit access setting.

Abstract: In a particular embodiment, a circuit device includes a translation look-aside buffer (TLB) configured to receive a virtual address and to translate the virtual address to a physical address of a cache having at least two partitions. The circuit device also includes a control logic circuit adapted to identify a partition replacement policy associated with the identified one of the at least two partitions based on a partition indicator. The control logic circuit controls replacement of data within the cache according to the identified partition replacement policy in response to a cache miss event.

Abstract: Systems and methods to perform fast rotation operations are disclosed. In a particular embodiment, a method includes executing a single instruction. The method includes receiving first data indicating a first coordinate and a second coordinate, receiving a first control value that indicates a first rotation value selected from a set of ninety degree multiples, and writing output data corresponding to the first data rotated by the first rotation value.

Abstract: An apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode are disclosed. In an embodiment, a method includes performing a first translation lookaside buffer (TLB) lookup based on a base address value to retrieve a speculative physical address. While performing the TLB lookup based on the base address value, the base address value is added to an offset value to generate an effective address value. The method also includes performing a comparison of the base address value and the effective address value based on a variable page size to determine whether the speculative physical address corresponds to the effective address.

Abstract: A method of processing data is disclosed that includes performing a fetch of a plurality of instructions from a memory unit. The method also includes grouping the plurality of instructions into packets of instructions of different types for parallel execution by a plurality of instruction execution units. The packets of instructions include a first instruction and a second instruction. The method includes using a combined scalar and vector condition code register to execute the first instruction for a compare operation and the second instruction for a conditional operation using the combined scalar and vector condition code register. The method also includes when the compare operation is a scalar compare operation, receiving a scalar compare instruction for the scalar compare operation at an instruction executing unit and storing results of the scalar compare operation in the combined scalar and vector condition code register.

Abstract: A system including a dual function adder is described. In one embodiment, the system includes an adder. The adder is configured for a first instruction to determine an address for a hardware prefetch if the first instruction is a hardware prefetch instruction. The adder is further configured for the first instruction to determine a value from an arithmetic operation if the first instruction is an arithmetic operation instruction.