Patents by Inventor Lucian COJOCAR
Lucian COJOCAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240354262Abstract: Aspects of the present disclosure relate to techniques for minimizing the effects of RowHammer and induced charge leakage. In examples, systems and methods for preventing access pattern attacks in random-access memory (RAM) are provided. In aspects, a data request associated with a page table may be determined to be a potential security risk and such potential security risk may be mitigated by randomly selecting a memory region from a subset of memory regions, copying data stored in a memory region associated with a page table entry in the page table to the second memory region, disassociating the second memory region from the subset of memory regions and associating the memory region associated with the page table to the second memory region, and updating the page table entry in the page table to refer to the second memory region.Type: ApplicationFiled: July 1, 2024Publication date: October 24, 2024Applicant: Microsoft Technology Licensing, LLCInventors: Stefan SAROIU, Alastair WOLMAN, Lucian COJOCAR, Kevin Robert LOUGHLIN
-
Patent number: 12061559Abstract: Aspects of the present disclosure relate to techniques for minimizing the effects of RowHammer and induced charge leakage. In examples, systems and methods for preventing access pattern attacks in random-access memory (RAM) are provided. In aspects, a data request associated with a page table may be determined to be a potential security risk and such potential security risk may be mitigated by randomly selecting a memory region from a subset of memory regions, copying data stored in a memory region associated with a page table entry in the page table to the second memory region, disassociating the second memory region from the subset of memory regions and associating the memory region associated with the page table to the second memory region, and updating the page table entry in the page table to refer to the second memory region.Type: GrantFiled: December 28, 2022Date of Patent: August 13, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Stefan Saroiu, Alastair Wolman, Lucian Cojocar, Kevin Robert Loughlin
-
Publication number: 20240031168Abstract: Various examples relate to an apparatus, device, method, and computer program for determining an integrity of a generated cryptographic signature. The apparatus is to generate, before generating the cryptographic signature, redundancy information of at least one cryptographic secret being used for generating the cryptographic signature, generate the cryptographic signature using the at least one cryptographic secret, compare, after generating the cryptographic signature, the redundancy information and the at least one cryptographic secret to determine whether the redundancy information matches the at least one cryptographic secret, and use the cryptographic signature if the redundancy information matches the at least one cryptographic secret.Type: ApplicationFiled: September 28, 2023Publication date: January 25, 2024Inventors: Yingchen WANG, Santosh GHOSH, Manoj SASTRY, Qian WANG, Lucian COJOCAR
-
Publication number: 20230129255Abstract: Aspects of the present disclosure relate to techniques for minimizing the effects of RowHammer and induced charge leakage. In examples, systems and methods for preventing access pattern attacks in random-access memory (RAM) are provided. In aspects, a data request associated with a page table may be determined to be a potential security risk and such potential security risk may be mitigated by randomly selecting a memory region from a subset of memory regions, copying data stored in a memory region associated with a page table entry in the page table to the second memory region, disassociating the second memory region from the subset of memory regions and associating the memory region associated with the page table to the second memory region, and updating the page table entry in the page table to refer to the second memory region.Type: ApplicationFiled: December 28, 2022Publication date: April 27, 2023Applicant: Microsoft Technology Licensing, LLCInventors: Stefan SAROIU, Alastair WOLMAN, Lucian COJOCAR, Kevin Robert LOUGHLIN
-
Patent number: 11567880Abstract: Aspects of the present disclosure relate to techniques for minimizing the effects of RowHammer and induced charge leakage. In examples, systems and methods for preventing access pattern attacks in random-access memory (RAM) are provided. In aspects, a data request associated with a page table may be determined to be a potential security risk and such potential security risk may be mitigated by randomly selecting a memory region from a subset of memory regions, copying data stored in a memory region associated with a page table entry in the page table to the second memory region, disassociating the second memory region from the subset of memory regions and associating the memory region associated with the page table to the second memory region, and updating the page table entry in the page table to refer to the second memory region.Type: GrantFiled: August 28, 2020Date of Patent: January 31, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Stefan Saroiu, Alastair Wolman, Lucian Cojocar, Kevin Robert Loughlin
-
Publication number: 20220050793Abstract: Aspects of the present disclosure relate to techniques for minimizing the effects of RowHammer and induced charge leakage. In examples, systems and methods for preventing access pattern attacks in random-access memory (RAM) are provided. In aspects, a data request associated with a page table may be determined to be a potential security risk and such potential security risk may be mitigated by randomly selecting a memory region from a subset of memory regions, copying data stored in a memory region associated with a page table entry in the page table to the second memory region, disassociating the second memory region from the subset of memory regions and associating the memory region associated with the page table to the second memory region, and updating the page table entry in the page table to refer to the second memory region.Type: ApplicationFiled: August 28, 2020Publication date: February 17, 2022Applicant: Microsoft Technology Licensing, LLCInventors: Stefan SAROIU, Alastair Wolman, Lucian COJOCAR, Kevin Robert LOUGHLIN
-
Patent number: 10978171Abstract: Aspects of the present disclosure relate to techniques for identifying susceptibility to induced charge leakage. In examples, a susceptibility test sequence comprising a cache line flush instruction is used to repeatedly activate a row of a memory unit. The susceptibility test sequence causes induced charge leakage within rows that are physically adjacent to the activated row, such that a physical adjacency map can be generated. In other examples, a physical adjacency map is used to identify a set of adjacent rows to a target row. A susceptibility test sequence is used to repeatedly activate the set of adjacent rows, after which the content of the target row is analyzed to determine whether the any bits of the target row flipped as a result of induced charge leakage. If flipped bits are not identified, an indication is generated that the memory unit is not susceptible to induced charge leakage.Type: GrantFiled: July 31, 2019Date of Patent: April 13, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Stefan Saroiu, Lucian Cojocar, Alastair Wolman
-
Publication number: 20210035654Abstract: Aspects of the present disclosure relate to techniques for identifying susceptibility to induced charge leakage. In examples, a susceptibility test sequence comprising a cache line flush instruction is used to repeatedly activate a row of a memory unit. The susceptibility test sequence causes induced charge leakage within rows that are physically adjacent to the activated row, such that a physical adjacency map can be generated. In other examples, a physical adjacency map is used to identify a set of adjacent rows to a target row. A susceptibility test sequence is used to repeatedly activate the set of adjacent rows, after which the content of the target row is analyzed to determine whether the any bits of the target row flipped as a result of induced charge leakage. If flipped bits are not identified, an indication is generated that the memory unit is not susceptible to induced charge leakage.Type: ApplicationFiled: July 31, 2019Publication date: February 4, 2021Applicant: Microsoft Technology Licensing, LLCInventors: Stefan SAROIU, Lucian COJOCAR, Alastair WOLMAN