Patents by Inventor Luciana Capello

Luciana Capello has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120191
    Abstract: A method is used for preparing the residue of a donor substrate, the residue comprising, on a peripheral zone of a main face, a peripheral ring. The method comprises: a first step of removing at least part of the peripheral ring; a second step of processing the main face of the residue aiming to remove a surface layer; a third step, after the second step, of grinding the peripheral zone of the main face of the residue, the third grinding step aiming to reduce the elevation of the peripheral zone.
    Type: Application
    Filed: February 14, 2022
    Publication date: April 11, 2024
    Inventors: Isabelle Huyet, Luciana Capello
  • Publication number: 20230005787
    Abstract: A handle substrate for a composite structure comprises a base substrate including an epitaxial layer of silicon on a monocrystalline silicon wafer obtained by Czochralski pulling, a passivation layer on and in contact with the epitaxial layer of silicon, and a charge-trapping layer on and in contact with the passivation layer. The monocrystalline silicon wafer of the base substrate exhibits a resistivity of between 10 and 500 ohm·cm, while the epitaxial layer of silicon exhibits a resistivity of greater than 2000 ohm·cm and a thickness ranging from 2 to 100 microns. The passivation layer is amorphous or polycrystalline. A method is described for forming such a substrate.
    Type: Application
    Filed: November 25, 2020
    Publication date: January 5, 2023
    Inventors: Young-Pil Kim, Daniel Delprat, Luciana Capello, Isabelle Bertrand, Frédéric Allibert
  • Publication number: 20220301847
    Abstract: A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.
    Type: Application
    Filed: June 2, 2022
    Publication date: September 22, 2022
    Inventors: Patrick Reynaud, Marcel Broekaart, Frédéric Allibert, Christelle Veytizou, Luciana Capello, Isabelle Bertrand
  • Patent number: 11373856
    Abstract: A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: June 28, 2022
    Assignee: Soitec
    Inventors: Patrick Reynaud, Marcel Broekaart, Frederic Allibert, Christelle Veytizou, Luciana Capello, Isabelle Bertrand
  • Publication number: 20200020520
    Abstract: A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.
    Type: Application
    Filed: January 11, 2018
    Publication date: January 16, 2020
    Inventors: Patrick Reynaud, Marcel Broekaart, Frederic Allibert, Christelle Veytizou, Luciana Capello, Isabelle Bertrand
  • Patent number: 10510531
    Abstract: A method of fabrication of a semiconductor element includes a step of rapid heat treatment in which a substrate comprising a base having a resistivity greater than 1000 Ohm·cm is exposed to a peak temperature sufficient to deteriorate the resistivity of the base. The step of rapid heat treatment is followed by a curing heat treatment in which the substrate is exposed to a curing temperature between 800° C. and 1250° C. and then cooled at a cooldown rate less than 5° C./second when the curing temperature is between 1250° C. and 1150° C., less than 20° C./second when the curing temperature is between 1150° C. and 1100° C., and less than 50° C./second when the curing temperature is between 1100° C. and 800° C.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: December 17, 2019
    Assignee: Soitec
    Inventors: Oleg Kononchuk, Isabelle Bertrand, Luciana Capello, Marcel Broekaart
  • Patent number: 10297464
    Abstract: A process for the manufacture of a semiconductor element includes a stage of rapid heat treatment of a substrate comprising a charge-trapping layer, which is capable of damaging an RF characteristic of the substrate. The rapid heat treatment stage is followed by a healing heat treatment of the substrate between 700° C. and 1,100° C., for a period of time of at least 15 seconds.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: May 21, 2019
    Assignee: Soitec
    Inventors: Marcel Broekaart, Luciana Capello, Isabelle Bertrand, Norbert Colombet
  • Publication number: 20180182640
    Abstract: A process for the manufacture of a semiconductor element includes a stage of rapid heat treatment of a substrate comprising a charge-trapping layer, which is capable of damaging an RF characteristic of the substrate. The rapid heat treatment stage is followed by a healing heat treatment of the substrate between 700° C. and 1100° C., for a period of time of at least 15 seconds.
    Type: Application
    Filed: June 1, 2016
    Publication date: June 28, 2018
    Inventors: Marcel Broekaart, Luciana Capello, Isabelle Bertrand, Norbert Colombet
  • Publication number: 20180130698
    Abstract: A method of fabrication of a semiconductor element includes a step of rapid heat treatment in which a substrate comprising a base having a resistivity greater than 1000 Ohm·cm is exposed to a peak temperature sufficient to deteriorate the resistivity of the base. The step of rapid heat treatment is followed by a curing heat treatment in which the substrate is exposed to a curing temperature between 800° C. and 1250° C. and then cooled at a cooldown rate less than 5° C./second when the curing temperature is between 1250° C. and 1150° C., less than 20° C./second when the curing temperature is between 1150° C. and 1100° C., and less than 50° C./second when the curing temperature is between 1100° C. and 800° C.
    Type: Application
    Filed: November 3, 2017
    Publication date: May 10, 2018
    Inventors: Oleg Kononchuk, Isabelle Bertrand, Luciana Capello, Marcel Broekaart
  • Patent number: 9198294
    Abstract: The invention relates to an electronic device for radiofrequency or power applications, comprising a semiconductor layer supporting electronic components on a support substrate, wherein the support substrate comprises a base layer having a thermal conductivity of at least 30 W/mK and a superficial layer having a thickness of at least 5 ?m, the superficial layer having an electrical resistivity of at least 3000 Ohm·cm and a thermal conductivity of at least 30 W/mK. The invention also relates to two processes for manufacturing such a device.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: November 24, 2015
    Assignee: SOITEC
    Inventors: Didier Landru, Luciana Capello, Eric Desbonnet, Christophe Figuet, Oleg Kononchuk
  • Publication number: 20130294038
    Abstract: The invention relates to an electronic device for radio frequency or power applications, comprising a semiconductor layer supporting electronic components on a support substrate, wherein the support substrate comprises a base layer having a thermal conductivity of at least 30 W/m K and a superficial layer having a thickness of at least 5 ?m, the superficial layer having an electrical resistivity of at least 3000 Ohm·cm and a thermal conductivity of at least 30 W/m K. The invention also relates to two processes for manufacturing such a device.
    Type: Application
    Filed: November 16, 2011
    Publication date: November 7, 2013
    Applicant: SOITEC
    Inventors: Didier Landru, Luciana Capello, Eric Desbonnet, Christophe Figuet, Oleg Kononchuk
  • Patent number: 7947571
    Abstract: The invention relates to a method for fabricating a semiconductor on insulator substrate, in particular a silicon on insulator substrate by providing a source substrate, providing a predetermined splitting area inside the source substrate by implanting atomic species, bonding the source substrate to a handle substrate, detaching a remainder of the source substrate from the source-handle component at the predetermined splitting area to thereby transfer a device layer of the source substrate onto the handle substrate, and thinning of the device layer. To obtain semiconductor on insulator substrates with a reduced Secco defect density of less than 100 per cm2 the implanting is carried out with a dose of less than 2.3×106 atoms per cm2 and the thinning is an oxidation step conducted at a temperature of less than 925° C.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: May 24, 2011
    Assignee: S.O.I. Tec Silicon on Insulator Technologies
    Inventors: Luciana Capello, Oleg Kononchuk, Eric Neyret, Alexandra Abbadie, Walter Schwarzenbach
  • Publication number: 20100052092
    Abstract: The invention relates to a method for fabricating a semiconductor on insulator substrate, in particular a silicon on insulator substrate by providing a source substrate, providing a predetermined splitting area inside the source substrate by implanting atomic species, bonding the source substrate to a handle substrate, detaching a remainder of the source substrate from the source-handle component at the predetermined splitting area to thereby transfer a device layer of the source substrate onto the handle substrate, and thinning of the device layer. To obtain semiconductor on insulator substrates with a reduced Secco defect density of less than 100 per cm2 the implanting is carried out with a dose of less than 2.3×106 atoms per cm2 and the thinning is an oxidation step conducted at a temperature of less than 925° C.
    Type: Application
    Filed: June 4, 2009
    Publication date: March 4, 2010
    Inventors: Luciana Capello, Oleg Kononchuk, Eric Neyret, Alexandra Abbadie, Walter Schwarzenbach