Abstract: Alternating copolymers having hydrocarbon-substituted terminal units and repeat units each containing two different monomer units with extreme ultraviolet (EUV)-absorbing elements are disclosed. Alternating copolymers having organic terminal units and repeat units each containing a monomer unit with an EUV-absorbing element and an organic monomer unit are also disclosed. A process of forming a polymer resist, which includes providing an alternating copolymer having repeat units with at least one EUV-absorbing monomer unit and replacing end groups of the alternating copolymer with unreactive terminal units, is disclosed as well.

Abstract: One or more embodiments described herein include systems, and/or methods that facilitate fabrication of a semiconductor device using a spacer lithography-etch process. According to an embodiment, a method can comprise performing a first lithography exposure and etch over a first layer of a semiconductor device, where the first lithography exposure and etch comprises forming one or more mandrels on a first region of a second layer by employing a first photoresist layer. The method can further comprise forming one or more spacers on a sidewall of the one or more mandrels and covering a second region of the second layer, where the second region is adjacent to the one or more mandrels. The method can further comprise forming a cut over a third region of the second layer and filling the third region with first material.

Abstract: Embodiments of present invention provide a method of forming an extreme ultraviolet (EUV) mask. The method includes subliming a radiation-sensitive material onto a surface of an EUV blank substrate; exposing the radiation-sensitive material to an ionizing radiation to form an EUV mask pattern; and removing a portion of the radiation-sensitive material from the surface of the EUV blank substrate where the portion of the radiation-sensitive material is unexposed to the ionizing radiation. An EUV mask made therefrom, and the related radiation-sensitive material are also provided.

Abstract: A method for forming a planarization layer is provided that can include depositing an organic planarization layer on a deposition surface using a spin on deposition method; and treating the deposited organic planarization layer with a solvent anneal. In some embodiments, a vapor of solvent is passed over the deposited organic planarization layer to increase uniformity of the deposited organic planarization layer. The method may further include curing the deposited organic planarization layer with a thermal anneal.

Abstract: Techniques for EUV resist pattern transfer using a graded hardmask are provided. In one aspect, a method of patterning is provided. The method includes: forming a graded hardmask on a device stack; depositing a resist onto the graded hardmask; patterning the resist to form a pattern in the resist having at least one feature; modifying at least one surface region to increase an etch rate of the graded hardmask; transferring the pattern from the resist to the graded hardmask; and transferring the pattern from the graded hardmask to at least one underlying layer of the device stack. A device structure formed by the patterning method is also provided.

Abstract: Techniques for using open frame (E0) exposures for lithographic tool track/cluster monitoring are provided. In one aspect, a method for monitoring a lithographic process includes: performing open frame exposures E0 of at least one wafer coated with a photoresist using a photolithography tool; baking and developing the at least one wafer; performing a defect inspection of the at least one wafer to generate a haze map; grouping haze data from the haze map; and analyzing the haze data to identify a maximum E0 response dose E?.

Abstract: Alternating copolymers having hydrocarbon-substituted terminal units and repeat units each containing two different monomer units with extreme ultraviolet (EUV)-absorbing elements are disclosed. Alternating copolymers having organic terminal units and repeat units each containing a monomer unit with an EUV-absorbing element and an organic monomer unit are also disclosed. A process of forming a polymer resist, which includes providing an alternating copolymer having repeat units with at least one EUV-absorbing monomer unit and replacing end groups of the alternating copolymer with unreactive terminal units, is disclosed as well.

Abstract: A photolithography patterning stack and method for repairing defects in the stack. The stack includes an organic planarization layer, a hardmask layer, and a plurality of patterned photoresist lines in contact with the hardmask layer. A plurality of trenches is situated between the plurality of patterned photoresist lines. Each trench exposes a portion of the hardmask layer. A repairing layer is formed in contact with and only bonded to surfaces of the plurality of patterned photoresist lines. The method includes forming a photolithographic patterning stack. The stack includes at least a hardmask layer formed on one or more underlayers and a photoresist layer formed in contact with the hardmask layer. The photoresist layer is patterned into a plurality of patterned portions. A repairing layer is formed in contact with and only bonded to surfaces of each patterned portion of the plurality of portions.

Abstract: Techniques for using open frame (E0) exposures for lithographic tool track/cluster monitoring are provided. In one aspect, a method for monitoring a lithographic process includes: performing open frame exposures E0 of at least one wafer coated with a photoresist using a photolithography tool; baking and developing the at least one wafer; performing a defect inspection of the at least one wafer to generate a haze map; grouping haze data from the haze map; and analyzing the haze data to identify a maximum E0 response dose E?.

Abstract: One or more embodiments described herein include systems, and/or methods that facilitate fabrication of a semiconductor device using a spacer lithography-etch process. According to an embodiment, a method can comprise performing a first lithography exposure and etch over a first layer of a semiconductor device, where the first lithography exposure and etch comprises forming one or more mandrels on a first region of a second layer by employing a first photoresist layer. The method can further comprise forming one or more spacers on a sidewall of the one or more mandrels and covering a second region of the second layer, where the second region is adjacent to the one or more mandrels. The method can further comprise forming a cut over a third region of the second layer and filling the third region with first material.

Abstract: Techniques for lithography process delay characterization and effective dose compensation are provided. In one aspect, a method of analyzing a lithography process includes: applying a photoresist to a wafer; performing a post-apply bake of the photoresist; patterning the photoresist with sequences of open frame base line exposures performed at doses of from about 92% E0 to about 98% E0, and ranges therebetween, at multiple fields of the wafer separated by intervening programmed delay intervals, wherein E0 is the photoresist dose-to-clear; performing a post-exposure bake of the photoresist; developing the photoresist; performing a full wafer inspection to generate a grayscale map of the wafer; and analyzing the grayscale map to determine whether the intervening programmed delay intervals had an effect on the open frame base line exposures during the lithography process. Exposure dose compensation can then be applied to maintain a constant effective dose.

Abstract: One or more embodiments described herein include systems, and/or methods that facilitate fabrication of a semiconductor device using a spacer lithography-etch process. According to an embodiment, a method can comprise performing a first lithography exposure and etch over a first layer of a semiconductor device, where the first lithography exposure and etch comprises forming one or more mandrels on a first region of a second layer by employing a first photoresist layer. The method can further comprise forming one or more spacers on a sidewall of the one or more mandrels and covering a second region of the second layer, where the second region is adjacent to the one or more mandrels. The method can further comprise forming a cut over a third region of the second layer and filling the third region with first material.

Abstract: Techniques for lithography process delay characterization and effective dose compensation are provided. In one aspect, a method of analyzing a lithography process includes: applying a photoresist to a wafer; performing a post-apply bake of the photoresist; patterning the photoresist with sequences of open frame base line exposures performed at doses of from about 92% E0 to about 98% E0, and ranges therebetween, at multiple fields of the wafer separated by intervening programmed delay intervals, wherein E0 is the photoresist dose-to-clear; performing a post-exposure bake of the photoresist; developing the photoresist; performing a full wafer inspection to generate a grayscale map of the wafer; and analyzing the grayscale map to determine whether the intervening programmed delay intervals had an effect on the open frame base line exposures during the lithography process. Exposure dose compensation can then be applied to maintain a constant effective dose.

Abstract: A method includes depositing a resist layer onto a hard mask layer to form a multi-layer patterning material film stack on a semiconductor substrate, directing patterning radiation onto the film stack to form a developed pattern in the resist layer and exposing the film stack to at least one gas precursor in connection with a sequential infiltration synthesis process. The film stack is configured to facilitate selective infiltration of the at least one gas precursor into the resist layer.

Abstract: A method includes depositing a resist layer onto a hard mask layer to form a multi-layer patterning material film stack on a semiconductor substrate, directing patterning radiation onto the film stack to form a developed pattern in the resist layer and exposing the film stack to at least one gas precursor in connection with a sequential infiltration synthesis process. The film stack is configured to facilitate selective infiltration of the at least one gas precursor into the resist layer.

Abstract: A method for selectively encapsulating embedded memory pillars in a semiconductor device includes coating a passivation layer on a first dielectric surface on a first outer dielectric layer present in the semiconductor device. The passivation layer adheres to the dielectric surface selective to metal. The method includes depositing an encapsulation layer on side and top surfaces of the embedded memory pillars. The passivation layer prevents deposition of the encapsulation layer on the first dielectric surface of the first outer layer dielectric. The method includes removing the first outer dielectric layer from horizontal subraces around the embedded memory pillar and the encapsulation layer from the top surface of the embedded memory pillars.

Abstract: A method includes forming a first insulating layer having one or more vias formed in at least a portion of the first insulating layer. The vias are filled with a first metallic material. A cap layer is deposited on a top surface of the first insulating layer and a top surface of the one or more vias and a second insulating layer is deposited on a top surface of the cap layer. One or more openings are formed in the second insulating layer and the cap layer. A self-assembled monolayer is formed on an exposed top surface of the first metallic material in the one or more vias. A barrier layer is formed on at least the exposed surface of the one or more openings. The self-assembled monolayer is removed and the one or more openings are filled with a second metallic material.

Abstract: Techniques for EUV resist pattern transfer using a graded hardmask are provided. In one aspect, a method of patterning is provided. The method includes: forming a graded hardmask on a device stack; depositing a resist onto the graded hardmask; patterning the resist to form a pattern in the resist having at least one feature; modifying at least one surface region to increase an etch rate of the graded hardmask; transferring the pattern from the resist to the graded hardmask; and transferring the pattern from the graded hardmask to at least one underlying layer of the device stack. A device structure formed by the patterning method is also provided.

Abstract: A vertical field-effect transistor and a method for fabricating the same. The vertical field-effect transistor includes a substrate and a bottom source/drain region. The vertical field-effect transistor also includes at least one fin structure, and further includes a bottom spacer layer. The bottom spacer layer has a substantially uniform thickness with a thickness variation of less than 3 nm. A gate structure contacts the bottom spacer layer and at least one fin structure. The method includes forming a structure including a substrate, a source/drain region, and one or more fins. A polymer brush spacer is formed in contact with at least sidewalls of the one or more fins. A polymer brush layer is formed in contact with at least the source/drain region and the polymer brush spacer. The polymer brush spacer is removed. Then, the polymer brush layer is reflowed to the sidewalls of the at least one fin.

Abstract: A method for selectively encapsulating embedded memory pillars in a semiconductor device includes coating a passivation layer on a first dielectric surface on a first outer dielectric layer present in the semiconductor device. The passivation layer adheres to the dielectric surface selective to metal. The method includes depositing an encapsulation layer on side and top surfaces of the embedded memory pillars. The passivation layer prevents deposition of the encapsulation layer on the first dielectric surface of the first outer layer dielectric. The method includes removing the first outer dielectric layer from horizontal subraces around the embedded memory pillar and the encapsulation layer from the top surface of the embedded memory pillars.