Abstract: A method of producing multiple models of a hardware (integrated circuit) design including: translating a master model of a design of the integrated circuit to at least first and second models that are functionally equivalent to the master model and that are at different levels of abstraction from each, other and in which each of the first and second models includes integrated circuit timing information that is accurate for its level of abstraction.

Abstract: A method of synthesis of multiple implementations of a design is provided comprising: translating a model of the design to a first output model compliant with first constraints; and translating the model of the design to a second output model compliant with second constraints.

Abstract: A method of producing multiple models of a hardware (integrated circuit) design including: translating a master model of a design of the integrated circuit to at least first and second models that are functionally equivalent to the master model and that are at different levels of abstraction from each, other and in which each of the first and second models includes integrated circuit timing information that is accurate for its level of abstraction.

Abstract: A method of synthesis of a model representing a design is provided comprising: inputting to a synthesis tool information representing a design at a level of abstraction; using a synthesis tool to automatically translate the information representing a design at a level of abstraction to a model representing the design at a lower level abstraction; and producing a record the information input to the tool representing the design at the level of abstraction.

Abstract: A combined language-compiler that provides for the efficient compilation process of hybrid computer code written using a plurality of computer languages by splitting the hybrid code in such a way that each code statement is optimally independently compliable. The designer specifies both computation and communication between different hybrid code modules.

Abstract: A method and system for evaluating performance level models of electronic systems having both hardware and software components is provided. The system and method allow for the simplified implementation and testing of several different architectural designs for compliance with the desired operational requirement of a designed electronic system.

Abstract: A combined language-compiler that provides for the efficient compilation process of hybrid computer code written using a plurality of computer languages by splitting the hybrid code in such a way that each code statement is optimally independently compilable. The designer specifies both computation and communication between different hybrid code modules.

Abstract: A method for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the method includes the steps of determining a set of gates in the circuit coupled to the first primary input lead, the set of gates coupled to a set of edges, determining the 1-controllability of each edge in the set of edges; providing a binary OR tree to the circuit; coupling the set of edges to the binary OR tree; providing an AND gate to the circuit; coupling the AND gate to the binary OR tree and to the first primary input lead; providing a binary AND tree to the circuit; uncoupling the first primary input leads from the set of gates; and coupling the binary AND tree to the AND gate, to the binary OR tree, and to the set of gates.

Abstract: A method for generating a low-power circuit from a Shannon graph having a plurality of primary inputs, a plurality of nodes including parent and child nodes, a first end-terminal, and a second end-terminal, each of the plurality of nodes having output edges associated therewith, includes the steps of: substituting the plurality of nodes and associated output edges with a plurality of cells, one cell for each node and output edge associated therewith, each cell including a plurality of elements; coupling a cell substituted for a parent node to cells substituted for child nodes of the parent node; and bypassing particular elements of child nodes having only one parent node.