Abstract: A communication unit (300, 400, 500) is described that includes at least one antenna (302, 402, 502); a plurality of radio frequency (RF) circuits (304, 310, 404, 410) respectively coupled to at least one antenna (302, 402, 502); at least one sigma-delta modulator (316, 416, 616, 816) comprising a number of stages, each stage comprising at least one signal-feedforward coefficient (603, 604, 605), a filter and a feedback gain element, the at least one sigma-delta modulator (316, 416, 616, 816) coupled to the plurality of RF circuits (304, 310, 404, 410) and configured to perform sigma-delta modulation; and a controller (340, 440, 640, 840) operably coupled to the at least one sigma-delta modulator (316, 416, 616, 816).

Abstract: A summing node is provided for summing a first and second differential signals. Each of the first and second differential signals comprise respective direct and inverse signal components. The summing node comprises a first differential transistor pair comprising a first and second input and coupled to a first and second output. The summing node further comprises a second differential transistor pair comprising a third and fourth input and coupled to the first and second output. The first and fourth inputs are respectively coupled to the direct and inverse signal components of the first differential signal and the second and third inputs are respectively coupled to the direct and inverse signal components of the second differential signal.

Abstract: Circuits and methods for jitter compensation in a receiver system are useful to improve performance. One such circuit includes a combiner block for combining a reference signal with an input signal (Sin) of the circuit, and a converter stage for converting the input signal (Sin) together with the reference signal. The converter stage is clocked by a clock signal modulated by a jitter signal. A forward path having a first mixer unit is provided for multiplying a copy of an output signal (A) of the converter stage with the frequency of the reference signal in order to generate a jitter compensating signal (B). A compensation unit for compensating jitter in the output signal (A) of the converter stage in a direct output path with the jitter compensating signal (B) is also provided.

Abstract: The present invention relates to a circuit and a method for jitter compensation in a receiver system and for improving the SNR and/or the BER performance. The circuit for jitter compensation comprises: a combiner block (600) for combining a reference signal with an input signal (Sin) of said circuit (700, 900, 1000); a converter stage (605) for converting said input signal (Sin) together with said reference signal, said converter stage (605) being clocked by a clock signal modulated by a jitter signal; a forward path (631) having a first mixer unit (610) for multiplying a copy of an output signal (A) of said converter stage (605) with the frequency of said reference signal for generating a jitter compensating signal (B); and a compensation unit (608) for compensating jitter in said output signal (A) of said converter stage (605) in a direct output path (632) with said jitter compensating signal (B).

Abstract: In an AD converter a primary ?A-modulator digitizes the analog input signal. The quantization noise generated thereby is isolated in the analog domain and digitized in a secondary ?A-modulator. The quantization noise so digitized by the secondary ?A-modulator is subtracted from the quantization noise in the output of the primary ?A-modulator. Because the quantization noise generated by the primary ?A-modulator is subject to filtering (shaping) the quantization noise digitized in the secondary ?A-modulator should also be filtered. This is performed by similar filtering in the feedback path of the secondary ?A-modulator.

Abstract: In a method for calibrating a multi-bit DAC intended, particularly, for application in high-speed and high-resolution ADCs, such as ? ? ADCs, and comprising a number of DAC cells, apart from the number of DAC cells applied in the multi-bit DAC for conversion, an additional DAC cell is provided, which can be interchanged with each of the other DAC cells in order to switch each DAC cell successively from the multi-bit DAC into a calibration circuit to calibrate said DAC cell without interrupting the conversion. The calibration circuit includes means for measuring errors in the DAC cell under calibration and means for correcting said DAC cell.

Abstract: The invention relates to a mixer circuit, a receiver comprising a mixer circuit, and a method of mixing an input signal with an oscillator signal. A mixer circuit 300 according to the invention comprises a first input node 301 and a second input node 302 for receiving an input signal Vin, a first output node 321 and a second output node 322, voltage to-current conversion means R1a, R1b, R2a, R2b, and switching means M1, M2, M3, M4 operatively coupled to each other and to the first input node 301, the second input 305 node 302, the first output node 321, and the second output node 322 to generate a mixed input signal the first output node 321 and the second output node 322 in response to an oscillator signal.

Abstract: The A/D converter has a digital output for outputting a digital output signal selected from a set of three or more available values. A feedback loop generates the digital output signal so that a time averaged difference between an analog input signal and an analog feedback signal representative of the digital output signal is minimized. A feedback signal generator generates successive signal levels of the feedback signal. A return to zero switch inserts predetermined return to zero levels between the signal levels in the feedback signal. The return to zero switch is also used to provide the signal level for one of the available values.

Abstract: A receive beamformer, and ultrasound system incorporating such a receive beamformer, is constructed to implement multi-bit analog to digital conversion in such a way that the need for gain control in the channel architecture preceding the digital conversion circuitry is obviated. Accordingly, the beamformer and any ultrasound system incorporating it may realize a rigorous level of ADC performance at desirable output rates, and a lower cost. Preferably, the invention construction realizes a level of performance by which CW Doppler may be digitized in the same manner as very wide-band pulsed-wave signals.