Abstract: Circuits and methods providing a electronic power supply applicable to any dual supply rail systems, which require a smooth and uninterrupted output supply and a replica power path and autonomous mode of operation from the system power supply are disclosed. In a preferred embodiment of the invention the power supply is applied to a real time clock. An Innovative Replica Power Path concept and circuit implementation ensures the smooth and uninterrupted transfer of power from one input source to the other. The circuit features a Latched Supply Comparator that guarantees the commutation to the Replica Power Path only happens after the voltage is settled. Zero power consumption from the back-up energy source is achieved in the presence of an alternative higher voltage source. The generated RTC supply voltage does not suffer from abrupt changes when the voltage level of the main system power source (battery or charger) is connected or disconnected.

Abstract: An apparatus and method for a system with improved power supply rejection ratio (PSRR) over a wide frequency range. The improved PSRR is achieved by negating the influence of the parasitic capacitance associated with the bias lines and the introduction of a regulated power supply with embodiments associated with providing a ripple free and regulated supply. With reduction of parasitic capacitance, and providing an ENABLE switch by a pre-regulated supply, the degradation of the PSRR is achieved. The embodiments include both n-channel and p-channel MOSFETs implementations, and a positive and negative regulated power supply voltage. With the combined influence of the utilization of the VREG supply, and the lowering of battery-to-bias line capacitance using design layout and improved floor planning an improved PSRR over a wide frequency distribution is achieved.

Abstract: Circuits and methods to improve dynamic load transient performance of circuits supplying high current and having parasitic resistances are disclosed. These circuits comprise e.g. LDOs, amplifiers or buffers. The circuits and methods are characterized by including parasitic resistances, caused by bond wires, metallization of pass devices, and substrate routings, in a loop for fast transient response. Furthermore the circuits comprise a stabilization circuit within said loop and a separate pad for said loop.

Abstract: Circuits and methods to maintain a resistive voltage divider ratio during start-up of an electronic circuit comprising a feed-forward capacitor across a feedback resistor using a dynamic start-up circuit are disclosed as e.g. a LDO or an amplifier. In a preferred embodiment of the disclosure is applied to an LDO. Modification of the resistive voltage divider ratio caused by the feed-forward capacitor during start-up is prevented while the voltage level of a voltage access point of the voltage divider on the feed-forward capacitor is maintained. A start-up circuit comprises a start-up capacitor and a start-up comparator.

Abstract: Circuits and methods to improve dynamic load transient performance of circuits supplying high current and having parasitic resistances are disclosed. These circuits comprise e.g. LDOs, amplifiers or buffers. The circuits and methods are characterized by including parasitic resistances, caused by bond wires, metallization of pass devices, and substrate routings, in a loop for fast transient response. Furthermore the circuits comprise a stabilization circuit within said loop and a separate pad for said loop.

Abstract: Circuits and methods to improve dynamic load transient performance of circuits supplying high current and having parasitic resistances are disclosed. These circuits comprise e.g. LDOs, amplifiers or buffers. The circuits and methods are characterized by including parasitic resistances, caused by bond wires, metallization of pass devices, and substrate routings, in a loop for fast transient response. Furthermore the circuits comprise a stabilization circuit within said loop and a separate pad for said loop.

Abstract: Circuits and methods to maintain a resistive voltage divider ratio during start-up of an electronic circuit comprising a feed-forward capacitor across a feedback resistor using a dynamic start-up circuit are disclosed as e.g. a LDO or an amplifier. In a preferred embodiment of the disclosure is applied to an LDO. Modification of the resistive voltage divider ratio caused by the feed-forward capacitor during start-up is prevented while the voltage level of a voltage access point of the voltage divider on the feed-forward capacitor is maintained. A start-up circuit comprises a start-up capacitor and a start-up comparator.

Abstract: Circuits and methods to achieve a clean start-up process and power saving of pulsed enabled electronic devices having an output capacitor and components requiring biasing during normal operating conditions are disclosed. These electronic devices could be e.g. LDOs, amplifiers or buffers. A set of switches are enabling bias currents from the output capacitor to internal nodes requiring biasing under normal operational conditions as e.g. output nodes of amplifying means.

Abstract: An apparatus and method for a system with improved power supply rejection ratio (PSRR) over a wide frequency range. The improved PSRR is achieved by negating the influence of the parasitic capacitance associated with the bias lines and the introduction of a regulated power supply with embodiments associated with providing a ripple free and regulated supply. With reduction of parasitic capacitance, and providing an ENABLE switch by a pre-regulated supply, the degradation of the PSRR is achieved. The embodiments include both n-channel and p-channel MOSFETs implementations, and a positive and negative regulated power supply voltage. With the combined influence of the utilization of the VREG supply, and the lowering of battery-to-bias line capacitance using design layout and improved floor planning an improved PSRR over a wide frequency distribution is achieved.

Abstract: Circuits and methods providing a electronic power supply applicable to any dual supply rail systems, which require a smooth and uninterrupted output supply and a replica power path and autonomous mode of operation from the system power supply are disclosed. In a preferred embodiment of the invention the power supply is applied to a real time clock. An Innovative Replica Power Path concept and circuit implementation ensures the smooth and uninterrupted transfer of power from one input source to the other. The circuit features a Latched Supply Comparator that guarantees the commutation to the Replica Power Path only happens after the voltage is settled. Zero power consumption from the back-up energy source is achieved in the presence of an alternative higher voltage source. The generated RTC supply voltage does not suffer from abrupt changes when the voltage level of the main system power source (battery or charger) is connected or disconnected.

Abstract: Circuits and methods providing a electronic power supply applicable to any dual supply rail systems, which require a smooth and uninterrupted output supply and a replica power path and autonomous mode of operation from the system power supply are disclosed. In a preferred embodiment of the invention the power supply is applied to a real time clock. An Innovative Replica Power Path concept and circuit implementation ensures the smooth and uninterrupted transfer of power from one input source to the other. The circuit features a Latched Supply Comparator that guarantees the commutation to the Replica Power Path only happens after the voltage is settled. Zero power consumption from the back-up energy source is achieved in the presence of an alternative higher voltage source. The generated RTC supply voltage does not suffer from abrupt changes when the voltage level of the main system power source (battery or charger) is connected or disconnected.

Abstract: Circuits and methods to achieve a clean start-up process and power saving of pulsed enabled electronic devices having an output capacitor and components requiring biasing during normal operating conditions are disclosed. These electronic devices could be e.g. LDOs, amplifiers or buffers. A set of switches are enabling bias currents from the output capacitor to internal nodes requiring biasing under normal operational conditions as e.g. output nodes of amplifying means.

Abstract: Circuits and methods to maintain a resistive voltage divider ratio during start-up of an electronic circuit comprising a feed-forward capacitor across a feedback resistor using a dynamic start-up circuit are disclosed as e.g. a LDO or an amplifier. In a preferred embodiment of the disclosure is applied to an LDO. Modification of the resistive voltage divider ratio caused by the feed-forward capacitor during start-up is prevented while the voltage level of a voltage access point of the voltage divider on the feed-forward capacitor is maintained. Embodiments of the disclosure presented comprise using a start-up buffer or a start-up capacitor during the start-up phase.

Abstract: Circuits and methods to improve dynamic load transient performance of circuits supplying high current and having parasitic resistances are disclosed. These circuits comprise e.g. LDOs, amplifiers or buffers. The circuits and methods are characterized by including parasitic resistances, caused by bond wires, metallization of pass devices, and substrate routings, in a loop for fast transient response. Furthermore the circuits comprise a stabilization circuit within said loop and a separate pad for said loop.

Abstract: A self-biased reference circuit device (100) includes a first cascode current mirror (116), a second cascode current mirror (118), and a startup circuit (108). The first cascode current mirror (116) is capable to generate a first bias voltage (136) and a second bias voltage (140) in response to a first current and to generate a second current in response to the first and second bias voltages. The second cascode current mirror (118) is capable to generate a third bias voltage (164) in response to the second current, to generate a fourth bias voltage (168) in response to a third current, and to generate the first current in response to the third and fourth bias voltages. The startup circuit includes a first switch (188) and a second switch (196). The first switch (188) is capable to connect the first bias voltage (136) and fourth bias voltage (168) during startup.

Abstract: Circuits and methods for power efficient generation of supply voltages and currents in an integrated circuit by reducing the power consumption of all core analog circuit blocks by a pulsed operation mode are disclosed. In a preferred embodiment of the invention the invention has been applied to a power management chip. Pulsed Mode of Operation of ALL core analog blocks—internal LDO/s, VREF an IBIAS generators, results in significantly reduced power consumption. New circuit realizations and control algorithms to improve the ON/OFF ratio of the Pulsed Mode Operation yield in better power efficiency. Innovative circuit implementation consisting of an additional Top Up Buffer Amplifier stage ensures a fast recharge of VREF output, thus allowing shorter ON times and respectively even better power efficiency. Bypassing a low bandwidth and slow to start LDO with a fast Bypass Comparator supplies a LDO rail in Pulsed Mode of operation.

Abstract: Circuits and methods providing a electronic power supply applicable to any dual supply rail systems, which require a smooth and uninterrupted output supply and a replica power path and autonomous mode of operation from the system power supply are disclosed. In a preferred embodiment of the invention the power supply is applied to a real time clock. An Innovative Replica Power Path concept and circuit implementation ensures the smooth and uninterrupted transfer of power from one input source to the other. The circuit features a Latched Supply Comparator that guarantees the commutation to the Replica Power Path only happens after the voltage is settled. Zero power consumption from the back-up energy source is achieved in the presence of an alternative higher voltage source. The generated RTC supply voltage does not suffer from abrupt changes when the voltage level of the main system power source (battery or charger) is connected or disconnected.

Abstract: A self-biased reference circuit device (100) includes a first cascode current mirror (116), a second cascode current mirror (118), and a startup circuit (108). The first cascode current mirror (116) is capable to generate a first bias voltage (136) and a second bias voltage (140) in response to a first current and to generate a second current in response to the first and second bias voltages. The second cascode current mirror (118) is capable to generate a third bias voltage (164) in response to the second current, to generate a fourth bias voltage (168) in response to a third current, and to generate the first current in response to the third and fourth bias voltages. The startup circuit includes a first switch (188) and a second switch (196). The first switch (188) is capable to connect the first bias voltage (136) and fourth bias voltage (168) during startup.

Abstract: Circuits and methods for power efficient generation of supply voltages and currents in an integrated circuit by reducing the power consumption of all core analog circuit blocks by a pulsed operation mode are disclosed. In a preferred embodiment of the invention the invention has been applied to a power management chip. Pulsed Mode of Operation of ALL core analog blocks—internal LDO/s, VREF an IBIAS generators, results in significantly reduced power consumption. New circuit realizations and control algorithms to improve the ON/OFF ratio of the Pulsed Mode Operation yield in better power efficiency. Innovative circuit implementation consisting of an additional Top Up Buffer Amplifier stage ensures a fast recharge of VREF output, thus allowing shorter ON times and respectively even better power efficiency. Bypassing a low bandwidth and slow to start LDO with a fast Bypass Comparator supplies a LDO rail in Pulsed Mode of operation.

Abstract: In one embodiment, a clock distribution chip includes a clock input adapted to receive an input clock signal, clock dividers each adapted to receive a clock signal based on the first input clock signal and to generate a divided clock signal, and programmable clock outputs adapted to provide output clock signals. The clock outputs are configurable to support a number of signaling standards. A programmable switch fabric is coupled between the clock dividers and the clock outputs and is configurable to provide the divided clock signals to the clock outputs.