Patents by Inventor Ludo Deferm
Ludo Deferm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6380039Abstract: A scaleable device concept and particularly a method for fabrication thereof is disclosed, which allows for a minimal well-controlled gate overlap by using low resistivity source/drain extension regions with shallow junctions. By using such shallow junctions, which are obtained using L-shaped spacers, the gate overlap is no longer dependent on the junction depth of the source/drain contact regions. Particularly the L-shaped spacers are used to locally reduce the penetration depth of the source/drain implantation in the substrate. This concept is particularly interesting for FET's having a channel length below 0.25 &mgr;m because this approach broadens the process window of the silicidation process of the source/drain contact regions. Moreover, the extension regions have to be subjected only to a limited thermal budget.Type: GrantFiled: April 1, 1999Date of Patent: April 30, 2002Assignee: Interuniversitair Microelektronica Centrum (IMEC VZW)Inventors: Goncal Badenes, Ludo Deferm, Stephan Beckx, Serge Vanhaelemeersch
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Patent number: 6282124Abstract: The present invention is a method for programming SSI cells or an array of said cells. The method achieves very fast programming while consuming only a very small amount of power, which paves the way for new applications such as battery-operated systems, page-mode programming for very high data throughput. The method also allows for the bitline voltage to be increased internally on the chip in order to circumvent the efficiency decrease associated with supply voltage scaling. By exploring the SSI mechanism in the subthreshold regime, an optimum value for the CG voltage is found for which the gate current is no longer maximized, but the energy consumed from the power supply is minimized and the injection efficiency during programming is maximized. The programming of a memory cell in this regime, where the gate current is a very steep function of the CG voltage, is, however, still achieved in a few microseconds while consuming only a very small cell current in the range of nanoamperes.Type: GrantFiled: June 7, 1999Date of Patent: August 28, 2001Assignee: Interuniversitair Microelektronica Centrum (IMEC, vzw)Inventors: Jan F. Van Houdt, Luc Haspeslagh, Ludo Deferm, Guido Groeseneken, Herman Maes
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Publication number: 20010012668Abstract: A scaleable device concept and particularly a method for fabrication thereof is disclosed, which allows for a minimal well-controlled gate overlap by using low resistivity source/drain extension regions with shallow junctions. By using such shallow junctions, which are obtained using L-shaped spacers, the gate overlap is no longer dependent on the junction depth of the source/drain contact regions. Particularly the L-shaped spacers are used to locally reduce the penetration depth of the source/drain implantation in the substrate. This concept is particularly interesting for FET's having a channel length below 0.25 &mgr;m because this approach broadens the process window of the silicidation process of the source/drain contact regions. Moreover, the extension regions have to be subjected only to a limited thermal budget.Type: ApplicationFiled: April 1, 1999Publication date: August 9, 2001Inventors: GONCAL BADENES, LUDO DEFERM, STEPHAN BECKX, SERGE VANHAELEMEERSCH
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Patent number: 6255227Abstract: The present invention relates to methods for controlling the etching rate of CoSi2 layers by adjusting the pH of an HF-based solution to obtain the desired etch rate. The pH of the HF-based solution may be adjusted by adding pH modifying chemicals to the solution. A further aspect of the invention is an improved method for manufacturing Schotky barrier infared detectors employing the controlled etching step. A method for reducing drain induced barrier lowering in an active transistor having a small gate length is also provided.Type: GrantFiled: January 6, 2000Date of Patent: July 3, 2001Assignee: Interuniversitair Microelektronica CentrumInventors: Ricardo Alves Donaton, Karen Irma Josef Maex, Rita Verbeeck, Philippe Jansen, Rita Rooyackers, Ludo Deferm, Mikhail Rodionovich Baklanov
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Patent number: 6153484Abstract: The present invention relates to methods for controlling the etching rate of CoSi.sub.2 layers by adjusting the pH of an HF-based solution to obtain the desired etch rate. The pH of the HF-based solution may be adjusted by adding pH modifying chemicals to the solution. A further aspect of the invention is an improved method for manufacturing Schottky barrier infared detectors employing the controlled etching step. A method for reducing drain induced barrier lowering in an active transistor having a small gate length is also provided.Type: GrantFiled: June 19, 1996Date of Patent: November 28, 2000Assignee: IMEC VZWInventors: Ricardo Alves Donaton, Karen Irma Josef Maex, Rita Verbeeck, Philippe Jansen, Rita Rooyackers, Ludo Deferm, Mikhail Rodionovich Baklanov
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Patent number: 6071825Abstract: The present invention relates to methods for fabricating Fully Overlapped Nitride-Etch Defined (Fond) devices. These methods permit the lateral dimension and depth of the lowly-doped source and drain extensions to be independently controlled and well defined.Type: GrantFiled: December 4, 1997Date of Patent: June 6, 2000Assignee: InterUniversitaire Microelektronica Centrum (IMEC VZW)Inventor: Ludo Deferm
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Patent number: 6044015Abstract: The present invention is a method for programming SSI cells or an array of said cells. The method achieves very fast programming while consuming only a very small amount of power, which paves the way for new applications such as battery-operated systems, page-mode programming for very high data throughput. The method also allows for the bitline voltage to be increased internally on the chip in order to circumvent the efficiency decrease associated with supply voltage scaling. By exploring the SSI mechanism in the subthreshold regime, an optimum value for the CG voltage is found for which the gate current is no longer maximized, but the energy consumed from the power supply is minimized and the injection efficiency during programming is maximized. The programming of a memory cell in this regime, where the gate current is a very steep function of the CG voltage, is, however, still achieved in a few microseconds while consuming only a very small cell current in the range of nanoamperes.Type: GrantFiled: August 9, 1996Date of Patent: March 28, 2000Assignee: Imec vzwInventors: Jan F. Van Houdt, Luc Haspeslagh, Ludo Deferm, Guido Groeseneken, Herman Maes
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Patent number: 5969991Abstract: The present invention is a method for programming SSI cells or an array of said cells. The method achieves very fast programming while consuming only a very small amount of power, which paves the way for new applications such as battery-operated systems, page-mode programming for very high data throughput. The method also allows for the bitline voltage to be increased internally on the chip in order to circumvent the efficiency decrease associated with supply voltage scaling. By exploring the SSI mechanism in the subthreshold regime, an optimum value for the CG voltage is found for which the gate current is no longer maximized, but the energy consumed from the power supply is minimized and the injection efficiency during programming is maximized. The programming of a memory cell in this regime, where the gate current is a very steep function of the CG voltage, is, however, still achieved in a few microseconds while consuming only a very small cell current in the range of nanoamperes.Type: GrantFiled: June 2, 1997Date of Patent: October 19, 1999Assignee: Interuniversitair Micro-Elektronica Centrum VZWInventors: Jan F. Van Houdt, Luc Haspeslagh, Ludo Deferm, Guido Groeseneken, Herman Maes