Patents by Inventor Ludovic Fourneaud

Ludovic Fourneaud has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230223277
    Abstract: An integrated circuit chip carrier includes a wall surrounding a cavity. The wall includes one or more levels where each level is formed from a layer of a resin around a block. The block is made of a material different from the resin. The block is removed to open the cavity.
    Type: Application
    Filed: January 9, 2023
    Publication date: July 13, 2023
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Fanny LAPORTE, Ludovic FOURNEAUD, Eric SAUGIER
  • Publication number: 20230187118
    Abstract: An integrated circuit device includes at least one inductive component with at least one integrated metal winding that is at least partially embedded in a coating. The coating includes at least one ferromagnetic material. The coating optionally includes a non-magnetic material, for example a dielectric.
    Type: Application
    Filed: December 5, 2022
    Publication date: June 15, 2023
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Tours) SAS
    Inventors: Ludovic FOURNEAUD, Laurent MOINDRON, Gregory BOUTELOUP
  • Publication number: 20220200117
    Abstract: A device for transmission of at least one high-frequency signal includes at least one first electrically-conductive track formed inside and/or on top of a flexible substrate.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 23, 2022
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Ludovic FOURNEAUD, Gregory BOUTELOUP, Jerome LOPEZ
  • Publication number: 20200355981
    Abstract: An electronic product having a silicon-on-insulator substrate, a porous layer of anodic oxide or anodic hydroxide over the silicon layer of the silicon-on-insulator substrate, and a metal layer over the porous layer and that defines at least one electrical transmission line. The velocity of the electrical signal in the at least one electrical transmission line may be controlled by appropriate configuration of the porosity ratio of the porous layer.
    Type: Application
    Filed: July 24, 2020
    Publication date: November 12, 2020
    Inventors: Frédéric Voiron, Julien El Sabahy, Ludovic Fourneaud
  • Patent number: 8994386
    Abstract: The invention relates to a method for measuring the permittivity and/or perviousness of a sample of a nonconductive material, said method comprising: a) measuring a value representative of an admittance Ytestco, b) measuring a value representative of an admittance Ytestcc only from the amplitude and the phase of the electromagnetic waves reflected onto an interface between the sample and the end of a second waveguide having at least one conductive web separated from a conductive sheath by a layer of dielectric material, said second waveguide also including a short circuit between the central web and the sheath at the interface with the sample, and c) calculating the permittivity of the sample from the values representative of the admittances Ytestco and Ytestcc and/or calculating the perviousness of the sample from the values representative of the admittances Ytestco and Ytestcc.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: March 31, 2015
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Ludovic Fourneaud, Laurent Dussopt
  • Publication number: 20120098554
    Abstract: The invention relates to a method for measuring the permittivity and/or perviousness of a sample of a nonconductive material, said method comprising: a) measuring (94) a value representative of an admittance Ytestco, measuring a (98) a value representative of an admittance Ytestcc only from the amplitude and the phase of the electromagnetic waves reflected onto an interface between the sample and the end of a second waveguide having at least one conductive web separated from a conductive sheath by a layer of dielectric material, said second waveguide also including a short circuit between the central web and the sheath at the interface with the sample, and c) calculating (100) the permittivity of the sample from the values representative of the admittances Ytestco and Ytestcc and/or calculating (100) the perviousness of the sample from the values representative of the admittances Ytestco and Ytestcc.
    Type: Application
    Filed: March 2, 2010
    Publication date: April 26, 2012
    Applicant: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Ludovic Fourneaud, Laurent Dussopt