Abstract: In accordance with a first aspect of the present disclosure, a radio frequency (RF) communication device is provided, comprising: a receiver unit configured to receive at least one radio frequency signal, wherein the receiver unit has a variable initial phase; a controller configured to change said initial phase; a measurement unit configured to measure a plurality of amplitudes and/or phases of the radio frequency signal, wherein each of said amplitudes and/or phases of the radio frequency signal corresponds to a different initial phase of the receiver unit. In accordance with a second aspect of the present disclosure, a corresponding method of operating an RF communication device is conceived.

Abstract: A digitally controlled DC-DC converter has a power stage coupled to an input voltage and to a control signal to generate an output voltage in response to the control signal. A controller generates the control signal and has an adjustment block to compare the output voltage to a reference voltage to generate a comparison signal, a logic circuit coupled to the adjustment block to receive the comparison signal and to generate the control signal in response to the comparison signal using a control word, and a digital-to analog converter coupled to the adjustment block, the power stage input voltage and the logic circuit to receive the control word from the logic circuit and to generate a converter voltage representing the control word using another voltage, the converter voltage being applied to the adjustment block to adjust the comparison signal.

Abstract: It is described a voltage regulator device (100), comprising: i) a power device (150), configured to receive an input signal (151) and to produce a corresponding output signal (152); ii) a comparator device (110), coupled via a feedback path (140) to the power device (150), and configured to receive the output signal (152) as a feedback signal (141), and to produce a compared feedback signal (112); and iii) a digital modulation device (120), arranged between the comparator device (110) and the power device (150), and configured to digitally modulate the compared feedback signal (112), and to provide the digitally modulated signal (121) to the power device (150), wherein the digital modulation device (120) comprises: iiia) a delta-sigma (122), iiib) a quantizer (124), and iiic) a feedforward path (128), configured to feedforward the compared feedback signal (112) beyond the delta-sigma (122).

Abstract: There is described a method of controlling a single inductor multiple output, SIMO, switching converter, the method comprising (a) counting, for each output of the multiple outputs of the SIMO switching converter, a period of time during which an output voltage at the respective output is below a corresponding individual threshold value, (b) identifying that output among the multiple outputs of the SIMO switching converter for which the counted period of time is longest, and (c) connecting the identified output to the single inductor of the SIMO switching converter to supply current from the single inductor of the SIMO switching converter to the identified output. Furthermore, a corresponding controller is described.

Abstract: An example apparatus includes power amplification circuitry and current-level switch circuitry. The power amplification circuitry has a first input port, a second input port, and field-effect transistor (FET) circuitry, the FET circuitry to operate in a saturation mode while drawing power provided at the first input port from a first power source. The current-level switch circuitry is to sense a change in a current-level used to maintain the FET circuitry in the saturation mode and, in response to the sensed change in the current-level, to cause the power amplification circuitry to draw power provided at the second input port from a second power source while maintaining the saturation mode of the FET circuitry.

Abstract: A chip includes a first pin coupled to a signal line and a controller to detect a state of the signal line using the first pin. The controller controls output of first power to the signal line through the first pin based on a first state of the signal line and prevents output of the first power to the signal line through the first pin based on a second state of the signal line. The signal line may be coupled to provide second power from a power source to a data storage device.

Abstract: Embodiments of a power amplifier and method of operating a power amplifier are disclosed. In one embodiment, a power amplifier includes a pulse wave modulation (PWM) controller, a first power control stage configured to drive a first output between VDD and VSS in response to a control signal from the PWM controller, a second power control stage configured to drive a second output between VDD and VSS in response to a control signal from the PWM controller, and a mid-voltage control circuit configured to hold the voltage of the first output at a mid-voltage that is between VDD and VSS during an interval between when the first output is driven between VDD and VSS and hold the voltage of the second output at the mid-voltage during an interval between when the first output is driven between VDD and VSS.

Abstract: An example apparatus includes power amplification circuitry and current-level switch circuitry. The power amplification circuitry has a first input port, a second input port, and field-effect transistor (FET) circuitry, the FET circuitry to operate in a saturation mode while drawing power provided at the first input port from a first power source. The current-level switch circuitry is to sense a change in a current-level used to maintain the FET circuitry in the saturation mode and, in response to the sensed change in the current-level, to cause the power amplification circuitry to draw power provided at the second input port from a second power source while maintaining the saturation mode of the FET circuitry.

Abstract: A device includes a first signal line, a second signal line, and a controller. The first signal line is coupled to a first storage area. The second signal line is coupled to a second storage area. The controller outputs a signal to the first signal line or the second signal line to select the first storage area or the second storage area. The first storage area may be a removable data storage card, and the second storage area may be an embedded storage area in the device. The signal is a reset signal for the selected one of the first storage area and the second storage area.

Abstract: A device includes a first signal line, a second signal line, and a controller. The first signal line is coupled to a first storage area. The second signal line is coupled to a second storage area. The controller outputs a signal to the first signal line or the second signal line to select the first storage area or the second storage area. The first storage area may be a removable data storage card, and the second storage area may be an embedded storage area in the device. The signal is a reset signal for the selected one of the first storage area and the second storage area.

Abstract: A chip includes a first pin coupled to a signal line and a controller to detect a state of the signal line using the first pin. The controller controls output of first power to the signal line through the first pin based on a first state of the signal line and prevents output of the first power to the signal line through the first pin based on a second state of the signal line. The signal line may be coupled to provide second power from a power source to a data storage device.

Abstract: A transmitter circuit includes first and second carrier signal generators for generating corresponding first and second digital carrier signals, each having the same frequency. Modulation circuitry determines a phase shift value based on a received modulation signal. Outphasing circuitry generates a first digital output signal by adding the phase shift value to the phase of the first digital carrier signal and generates a second digital output signal by subtracting the phase shift value from the phase of the second digital carrier signal. A first switched-capacitor digital-to-analog converter (DAC) receives the first digital output signal and generates a first analog antenna output signal. A second switched-capacitor DAC receives the second digital output signal and generates a second analog antenna output signal. The sampling phases of the first and second DACs are opposite one another, whereby the first and second analog antenna output signals form a time-interleaved antenna output signal.

Abstract: Embodiments of a power amplifier and method of operating a power amplifier are disclosed. In one embodiment, a power amplifier includes a pulse wave modulation (PWM) controller, a first power control stage configured to drive a first output between VDD and VSS in response to a control signal from the PWM controller, a second power control stage configured to drive a second output between VDD and VSS in response to a control signal from the PWM controller, and a mid-voltage control circuit configured to hold the voltage of the first output at a mid-voltage that is between VDD and VSS during an interval between when the first output is driven between VDD and VSS and hold the voltage of the second output at the mid-voltage during an interval between when the first output is driven between VDD and VSS.

Abstract: A transmitter circuit includes first and second carrier signal generators for generating corresponding first and second digital carrier signals, each having the same frequency Modulation circuitry determines a phase shift value based on a received modulation signal. Outphasing circuitry generates a first digital output signal by adding the phase shift value to the phase of the first digital carrier signal and generates a second digital output signal by subtracting the phase shift value from the phase of the second digital carrier signal. A first switched-capacitor digital-to-analog converter (DAC) receives the first digital output signal and generates a first analog antenna output signal. A second switched-capacitor DAC receives the second digital output signal and generates a second analog antenna output signal. The sampling phases of the first and second DACs are opposite one another, whereby the first and second analog antenna output signals form a time-interleaved antenna output signal.

Abstract: The present application relates to a power supply module which is operable in a switch mode and in a linear mode. The power supply module includes a detector for detecting the presence of an inductor at an output node of the power supply module If an inductor is detected, the detector outputs a signal indicating the presence of the inductor, and the power supply module selects the switch mode as its operating mode. If no inductor is detected, the detector outputs a signal indicative of the absence of an inductor and the power supply module selects its linear mode as its operating mode.

Abstract: A drain extended MOS transistor configured to operate in a gate-depletion regime. Devices comprising such transistors are described together with fabrication processes for such devices and transistors.

Abstract: A drain extended MOS transistor configured to operate in a gate-depletion regime. Devices comprising such transistors are described together with fabrication processes for such devices and transistors.

Abstract: A drain extended MOS transistor configured to operate in a gate-depletion regime. Devices comprising such transistors are described together with fabrication processes for such devices and transistors.

Abstract: A voltage converter includes a power switch having respective charging and discharging control terminals, and an output terminal coupled to a series connected inductor and capacitor. The voltage converter also includes a charging switch coupled to the charging control terminal of the power switch, a discharging switch coupled to the discharging control terminal of the power switch, and a feedback circuit coupling the power switch, charging switch and discharging switch to a node at which the capacitor and inductor are connected. During a charging phase, the charging switch couples the capacitor to the charging control terminal of the power switch, and during a discharging phase, the discharging switch couples the capacitor to the discharging control terminal of the power switch.

Abstract: A voltage supply circuitry is capable of coupling to wired audio headset circuitry and configurable to operate in a first mode, wherein the voltage supply circuitry provides a voltage supply to the wired audio headset functionality circuitry. The voltage supply circuitry is further capable of coupling to visual indication circuitry and further configurable to operate in a second mode, wherein the voltage supply circuitry provides a voltage supply to the visual indication circuitry.