Abstract: An asynchronous frame receiver includes an input for receiving an asynchronous frame comprising a break character, which includes a determined number of bits having a same value. A hot-plugging circuit for connecting to an asynchronous data bus that is operating by detecting the break character, and leaving an initial idle state and switching to at least one operating mode when the break character has been detected.

Abstract: An asynchronous data transmission device includes a data reception terminal receiving data clocked by a sampling signal in synchronization with a local clock signal. A register is connected to the data reception terminal for receiving the data. A clock deviation measuring circuit is connected to the register for determining a number M of periods of the sampling signal appearing during K periods of a synchronization signal received on the data reception terminal, and for comparing the number M to a tolerance margin defined by a lower threshold and an upper threshold.

Abstract: An integrated circuit having a clock calibration device receiving a local clock signal from an oscillator and applying a correction value to the signal to produce a corrected clock signal. The clock calibration device includes a frequency dividing module having a programmable divider and a calibration register for storing the correction value, the programmable divider receiving the local clock signal and delivering the corrected clock signal, and a circuit for determining a new correction value using an external reference signal. A time base unit produces a time base signal using a timing signal derived from the local clock signal, and it includes a counting module coupled to a load register wherein a load value is stored that determines the ratio between the frequency of the time base signal and that of the timing signal. An external computing unit loads a new load value into the load register by using the new correction value stored in the calibration register to deduce the new load value therefrom.

Abstract: A programmable clock generator delivers, using a primary clock signal of determined frequency, a first clock signal the frequency of which is equal to the frequency of the primary clock signal divided by a set point M. The set point M is a decimal number comprising a whole part M1 and a decimal part M2 and the clock generator modulates the period of the pulses of the first clock signal so that the duration of Ni successive pulses is substantially equal to M*Ni times the period of the primary clock signal, Ni being a reference number for modulating the period of the pulses of the first clock signal.

Abstract: A microprocessor includes a counter having a counting input and a reset input. The counting input is coupled to a first terminal of the microprocessor for the selection of an operating mode thereof by application of a predetermined number of pulses to the first terminal. The reset input of the counter is driven by a control signal present on a second terminal of the microprocessor. The control signal is maintained by default at a first logic value ensuring the maintaining at zero of the counter during the initialization period by a circuit internal or external the microprocessor. Immunity against electromagnetic perturbations causing the microprocessor to enter into the test mode is provided.

Abstract: A smart card reader includes a housing for receiving a smart card, a microprocessor, and a connector for connecting the microprocessor to the received smart card for establishing communications therebetween. A voltage source provides a power supply voltage to the microprocessor based upon the smart card being received in the housing. The smart card reader further includes a first switch interposed between the voltage source and a power supply terminal of the microprocessor. The first switch is closed when the received smart card is at an end of travel in the housing so that the power supply voltage is provided to the microprocessor, and is opened when the received smart card is no longer at the end of travel in the housing so that the power supply voltage is not provided to the microprocessor.

Abstract: A device for receiving asynchronous frames beginning with a header field, the device including a circuit for switching into a stand-by mode, a circuit for recognizing a header field, and a circuit for leaving the stand-by mode when a valid header field is recognized, the stand-by mode including the filtering of at least one signal likely to be emitted by the receiver device during the reception of a header field. The device is suitable in particular for UART circuits that are present in microcontrollers.

Abstract: An integrated circuit having a clock calibration device receiving a local clock signal from an oscillator and applying a correction value to the signal to produce a corrected clock signal. The clock calibration device includes a frequency dividing module having a programmable divider and a calibration register for storing the correction value, the programmable divider receiving the local clock signal and delivering the corrected clock signal, and a circuit for determining a new correction value using an external reference signal. A time base unit produces a time base signal using a timing signal derived from the local clock signal, and it includes a counting module coupled to a load register wherein a load value is stored that determines the ratio between the frequency of the time base signal and that of the timing signal. An external computing unit loads a new load value into the load register by using the new correction value stored in the calibration register to deduce the new load value therefrom.

Abstract: An asynchronous frame receiver includes an input for receiving an asynchronous frame comprising a break character, which includes a determined number of bits having a same value. A hot-plugging circuit for connecting to an asynchronous data bus that is operating by detecting the break character, and leaving an initial idle state and switching to at least one operating mode when the break character has been detected.

Abstract: A asynchronous frame receiver includes an input for receiving asynchronous frames. The asynchronous frames include standard characters, and a header that has a data bit length greater than a data bit length of the standard characters. A break character detection unit detects the break character. A standard character processing unit for detecting the standard characters is activated by the break character detection unit based upon the break character being detected.

Abstract: An asynchronous data transmission device includes a data reception terminal receiving data clocked by a sampling signal in synchronization with a local clock signal. A register is connected to the data reception terminal for receiving the data. A clock deviation measuring circuit is connected to the register for determining a number M of periods of the sampling signal appearing during K periods of a synchronization signal received on the data reception terminal, and for comparing the number M to a tolerance margin defined by a lower threshold and an upper threshold.

Abstract: A smart card reader includes a housing for receiving a smart card, a microprocessor, and a connector for connecting the microprocessor to the received smart card for establishing communications therebetween. A voltage source provides a power supply voltage to the microprocessor based upon the smart card being received in the housing. The smart card reader further includes a first switch interposed between the voltage source and a power supply terminal of the microprocessor. The first switch is closed when the received smart card is at an end of travel in the housing so that the power supply voltage is provided to the microprocessor, and is opened when the received smart card is no longer at the end of travel in the housing so that the power supply voltage is not provided to the microprocessor.

Abstract: A smart card reader includes a housing for receiving a smart card, a microprocessor, and a connector for connecting the microprocessor to the received smart card for establishing communications therebetween. A voltage source provides a power supply voltage to the microprocessor based upon the smart card being received in the housing. The smart card reader further includes a first switch interposed between the voltage source and a power supply terminal of the microprocessor. The first switch is closed when the received smart card is at an end of travel in the housing so that the power supply voltage is provided to the microprocessor, and is opened when the received smart card is no longer at the end of travel in the housing so that the power supply voltage is not provided to the microprocessor.

Abstract: A programmable clock generator delivers, using a primary clock signal of determined frequency, a first clock signal the frequency of which is equal to the frequency of the primary clock signal divided by a set point M. The set point M is a decimal number comprising a whole part M1 and a decimal part M2 and the clock generator modulates the period of the pulses of the first clock signal so that the duration of Ni successive pulses is substantially equal to M*Ni times the period of the primary clock signal, Ni being a reference number for modulating the period of the pulses of the first clock signal.

Abstract: A microprocessor includes a counter having a counting input and a reset input. The counting input is coupled to a first terminal of the microprocessor for the selection of an operating mode thereof by application of a predetermined number of pulses to the first terminal. The reset input of the counter is driven by a control signal present on a second terminal of the microprocessor. The control signal is maintained by default at a first logic value ensuring the maintaining at zero of the counter during the initialization period by a circuit internal or external the microprocessor. Immunity against electromagnetic perturbations causing the microprocessor to enter into the test mode is provided.

Abstract: A smart card reader includes a housing for receiving a smart card, a microprocessor, and a connector for connecting the microprocessor to the received smart card for establishing communications therebetween. A voltage source provides a power supply voltage to the microprocessor based upon the smart card being received in the housing. The smart card reader further includes a first switch interposed between the voltage source and a power supply terminal of the microprocessor. The first switch is closed when the received smart card is at an end of travel in the housing so that the power supply voltage is provided to the microprocessor, and is opened when the received smart card is no longer at the end of travel in the housing so that the power supply voltage is not provided to the microprocessor.

Abstract: The invention relates to a digital timer (20) comprising a binary counter (21) driven by a counting clock signal (Hc), the counter (21) presenting a stabilization time after each counting pulse, and means for delivering a detection signal (DS2) with a predetermined value when a counting order (N) is reached by the counter. According to the invention, the timer comprises wired logic means (22) arranged for detecting, at the output of the counter, a counting value (N−1) which is immediately before the counting order (N) in relation to the counting direction, and delivering an intermediate signal (DS1) with a predetermined value, as well means (24) for sampling the intermediate signal (DS1) at a moment when the counter receives the next counting pulse.