Abstract: A method for forming an implant hard mask on a substrate provides a multi-layer hardmask resistant to high processing temperatures and ion energies. In some embodiments, the method may comprise depositing a screen layer of oxide material with a thickness of approximately 20 nm to approximately 100 nm, depositing a first layer of the implant hard mask of amorphous carbon with a second thickness of approximately 100 nm to approximately 3000 nm; depositing a second layer of the implant hard mask of oxide with a third thickness of approximately 100 nm to approximately 3000 nm; depositing a photoresist layer on the second layer of the implant hard mask, and patterning the photoresist layer to expose portions of the second layer of the implant hard mask, etching the second layer of the implant hard mask and then the first layer of the implant hard mask using a hard mask etch process to expose portions of the screen layer.

Abstract: Disclosed herein are methods for forming MOSFET trenches with improved corner properties. In some embodiments, a method may include providing a device structure including an epitaxial layer and a hard mask over the epitaxial layer, and forming a trench through the well and the epitaxial layer, wherein the trench is defined by a sidewall, a bottom, and a corner at an intersection of the sidewall and the bottom. The method may further include implanting the device structure by delivering ions into the corner and into the bottom of the trench, and etching the trench to increase rounding of the corner.

Abstract: A silicon carbide transistor may be formed with a channel that includes a p-doped region between n-doped source and drain regions. A counter-doped region may be formed at the top of the channel directly underneath the gate oxide. Instead of using the conventional doping levels for the p-doped region, the doping concentration may be increase to be greater than about 1e18 cm3. The transistor may also include pocket regions on one or both sides of the channel. The pocket regions may be formed in the counter-doped region and may extend up to the gate oxide. These improvements individually and/or in combination may increase the current in the channel of the transistor without significantly increasing the threshold voltage beyond acceptable operating limits.