Abstract: An error supervision circuit for a non-encoded binary bit stream running through an elastic store comprising a memory having n locations, the bit rate of the stream supplied to the input of the memory differing from the bit rate of the stream produced at the output thereof. The successive bits in each group of n bits of the input stream are respectively written into the respective memory locations by write clock pulses supplied by a write register, at the input rate, and are successively read out from such locations by read clock pulses supplied by a read register at the output rate. The higher rate register is periodically interrupted for one or more bit periods to equalize filling and emptying of the memory. The bit streams at the input and output of the memory are supplied to respective data inputs of a comparator. A clock output of the lower rate register is connected to a first control input of the comparator to intermittently open a time window therein for receiving n bits of the lower rate bit stream.

Abstract: A clamping circuit for a television transmission system, includes an input amplifier whose non-inverting input is connected to the input of the clamping circuit and whose output is connected to the output of the clamping circuit. A negative feedback loop is provided between the output of the clamping circuit and the inverting input of the input amplifier, the negative feedback loop including the series arrangement of a sample and hold circuit and two amplifiers functioning as integrators. A switchable filter switched by the same pulse which switches the sample and hold circuit is provided between the output of the clamping circuit and the signal input terminal of the sample and hold circuit.