Patents by Inventor Ludwid Leipold

Ludwid Leipold has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrable buffer circuit for voltage level conversion having clamping means
    Patent number: 4801824
    Abstract: A signal voltage (E) based upon a supply voltage must be converted to a signal voltage (A) with ground reference so as to enable further processing in a logic circuit. A simple level converter comprises a series connection of a MOSFET (T1) connected to the supply voltage; the MOSFET also comprises a resistor (T2). The source terminal of the MOSFET (T1) is located at the potential of the supply voltage. The voltage to be converted is applied between the gate terminal and the source terminal, and the converted voltage occurs at the resistor (T2). The two voltages are each limited by one Zener diode (D2, D1).
    Type: Grant
    Filed: July 21, 1987
    Date of Patent: January 31, 1989
    Assignee: Siemens Aktiengesellschaft
    Inventors: Christine Fellinger, Josef Einzinger, Ludwid Leipold, Jenoe Tihanyi, Roland Weber