Patents by Inventor Luigi Esposito
Luigi Esposito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11922069Abstract: Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.Type: GrantFiled: May 20, 2022Date of Patent: March 5, 2024Assignee: Micron Technology, Inc.Inventors: Alberto Sassara, Giuseppe D'Eliseo, Lalla Fatima Drissi, Luigi Esposito, Paolo Papa, Salvatore Del Prete, Xiangang Luo, Xiaolai Zhu
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Publication number: 20240069741Abstract: Methods, systems, and devices for dynamic wear leveling techniques are described. A memory system may determine a type of data associated with data to be written to a block of the memory system. The memory system may determine the type of data based on a value of a counter associated with a segment of a mapping of the memory system that includes a logical address of the data. Additionally, or alternatively, the memory system may determine the type of data based on determining a quantity of invalid data in a set of recently selected (e.g., opened) blocks of the memory system. The memory system may select the block for storing the data based on the type of data and a quantity of times that the block has been erased and write the data to the selected block.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Inventors: Luigi Esposito, Paolo Papa
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Patent number: 11907556Abstract: Methods, systems, and devices for data relocation operation techniques are described. A memory system may include blocks of memory cells, for example, within a non-volatile memory device of the memory system. The memory system may identify a command to perform a data relocation operation associated with a block of memory cells and may select between a first procedure and a second procedure for performing the data relocation operation. The memory system may select between the first procedure and the second procedure based on whether one or more parameters associated with the data relocation operation satisfy a threshold. For example, the memory system may select the first procedure if the one or more parameters satisfy the threshold and may select the second procedure if the one or more parameters do not satisfy the threshold. The memory system may perform the data relocation operation using the selected procedure.Type: GrantFiled: January 20, 2022Date of Patent: February 20, 2024Assignee: Micron Technology, Inc.Inventors: Paolo Papa, Luigi Esposito, Massimo Iaculo, Giuseppe D'Eliseo, Alberto Sassara, Carminantonio Manganelli, Salvatore Del Prete
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Publication number: 20230376245Abstract: Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.Type: ApplicationFiled: May 20, 2022Publication date: November 23, 2023Inventors: Alberto Sassara, Giuseppe D'Eliseo, Lalla Fatima Drissi, Luigi Esposito, Paolo Papa, Salvatore Del Prete, Xiangang Luo, Xiaolai Zhu
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Patent number: 11705201Abstract: Devices and techniques for managing flash memory are disclosed herein. A memory controller may receive a first program request comprising first host data to be written to the flash memory. The flash memory may comprise a number of storage units with each storage unit comprising a number of storage sub-units. If the first host data is less than a remainder threshold, the memory controller may generate a first program data unit comprising the first host data and first log data describing the flash memory. The memory controller may program the program data unit to the first storage unit of the flash memory, where the first log data is written to a first storage sub-unit of the number of storage sub-unit. The memory controller may also store an indication that the first storage sub-unit is invalid.Type: GrantFiled: August 23, 2021Date of Patent: July 18, 2023Assignee: Micron Technology, Inc.Inventors: Paolo Papa, Luigi Esposito, Massimo Iaculo, Eric Kwok Fung Yuen, Gerard J. Perdaems
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Patent number: 11698826Abstract: Devices and techniques for fatal error logging in a memory device are described herein. For example, a read request can be received for a component of the memory device. A fatal error indication of an error that prevents correct execution of read request can be detected. Diagnostic information for the failure indication can be collected. A response to the read request can then be made with a portion of the diagnostic information as payload instead of the user data that would have occupied the payload had the read succeeded. Metadata in the response can be used to communicate an error code.Type: GrantFiled: August 30, 2021Date of Patent: July 11, 2023Assignee: Micron Technology, Inc.Inventors: Luigi Esposito, Paolo Papa, Massimo Iaculo, Erika Morvillo
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Patent number: 11662935Abstract: Methods, systems, and devices for improved data management for memory are described. An apparatus may include a memory array including one or more blocks of memory cells. Data read from a block of memory cells may be written to a buffer, to support providing the data to a host system or modification of the data by the host system. If a quantity of read commands performed at the block of memory cells satisfies a threshold, the data may be written from the buffer to a different block of memory cells, rather than the block from which the data was previously read.Type: GrantFiled: August 12, 2021Date of Patent: May 30, 2023Assignee: Micron Technology, Inc.Inventors: Luigi Esposito, Alberto Sassara, Paolo Papa, Massimo Iaculo
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Patent number: 11663120Abstract: Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.Type: GrantFiled: November 8, 2021Date of Patent: May 30, 2023Assignee: Micron Technology, Inc.Inventors: Giuseppe D'Eliseo, Luigi Esposito, Xinghui Duan, Lucia Santojanni, Massimo Iaculo
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Patent number: 11650931Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.Type: GrantFiled: April 19, 2021Date of Patent: May 16, 2023Assignee: Micron Technology, Inc.Inventors: Carminantonio Manganelli, Yoav Weinberg, Alberto Sassara, Paolo Papa, Luigi Esposito, Giuseppe D'Eliseo, Angelo Della Monica, Massimo Iaculo
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Publication number: 20230048133Abstract: Methods, systems, and devices for improved data management for memory are described. An apparatus may include a memory array including one or more blocks of memory cells. Data read from a block of memory cells may be written to a buffer, to support providing the data to a host system or modification of the data by the host system. If a quantity of read commands performed at the block of memory cells satisfies a threshold, the data may be written from the buffer to a different block of memory cells, rather than the block from which the data was previously read.Type: ApplicationFiled: August 12, 2021Publication date: February 16, 2023Inventors: Luigi Esposito, Alberto Sassara, Paolo Papa, Massimo Iaculo
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Publication number: 20220406388Abstract: Methods, systems, and devices for setting switching for single-level cells (SLCs) are described. A memory system may receive an access command from a host. The access command may correspond to an SLC block or to a multiple-level cell block. If the access command corresponds to an SLC block, the memory system may modify the access command to include one or more bits indicating a setting to use for performing the access operation corresponding to the access command. The setting may define one or more operating parameters for performing the access operation. The memory system may use bits to indicate the setting that are used to indicate a page address for multiple-level cell blocks. The memory system may issue the access command to a memory device, which may perform the access operation using the setting indicated in the one or more bits included by the memory system.Type: ApplicationFiled: May 4, 2022Publication date: December 22, 2022Inventors: Umberto Siciliani, Tao Liu, Ting Luo, Dionisio Minopoli, Giuseppe D'Eliseo, Giuseppe Ferrari, Walter Di'Francesco, Antonino Pollio, Luigi Esposito, Anna Scalesse, Allison J. Olson, Anna Chiara Siviero
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Publication number: 20220261153Abstract: Methods, systems, and devices for data relocation operation techniques are described. A memory system may include blocks of memory cells, for example, within a non-volatile memory device of the memory system. The memory system may identify a command to perform a data relocation operation associated with a block of memory cells and may select between a first procedure and a second procedure for performing the data relocation operation. The memory system may select between the first procedure and the second procedure based on whether one or more parameters associated with the data relocation operation satisfy a threshold. For example, the memory system may select the first procedure if the one or more parameters satisfy the threshold and may select the second procedure if the one or more parameters do not satisfy the threshold. The memory system may perform the data relocation operation using the selected procedure.Type: ApplicationFiled: January 20, 2022Publication date: August 18, 2022Inventors: Paolo Papa, Luigi Esposito, Massimo Iaculo, Giuseppe D'Eliseo, Alberto Sassara, Carminantonio Manganelli, Salvatore Del Prete
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Publication number: 20220066926Abstract: Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.Type: ApplicationFiled: November 8, 2021Publication date: March 3, 2022Inventors: Giuseppe D'Eliseo, Luigi Esposito, Xinghui Duan, Lucia Santojanni, Massimo Iaculo
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Publication number: 20220012117Abstract: Devices and techniques for fatal error logging in a memory device are described herein. For example, a read request can be received for a component of the memory device. A fatal error indication of an error that prevents correct execution of read request can be detected. Diagnostic information for the failure indication can be collected. A response to the read request can then be made with a portion of the diagnostic information as payload instead of the user data that would have occupied the payload had the read succeeded. Metadata in the response can be used to communicate an error code.Type: ApplicationFiled: August 30, 2021Publication date: January 13, 2022Inventors: Luigi Esposito, Paolo Papa, Massimo Iaculo, Erika Morvillo
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Publication number: 20210383872Abstract: Devices and techniques for managing flash memory are disclosed herein. A memory controller may receive a first program request comprising first host data to be written to the flash memory. The flash memory may comprise a number of storage units with each storage unit comprising a number of storage sub-units. If the first host data is less than a remainder threshold, the memory controller may generate a first program data unit comprising the first host data and first log data describing the flash memory. The memory controller may program the program data unit to the first storage unit of the flash memory, where the first log data is written to a first storage sub-unit of the number of storage sub-unit, The memory controller may also store an indication that the first storage sub-unit is invalid.Type: ApplicationFiled: August 23, 2021Publication date: December 9, 2021Inventors: Paolo Papa, Luigi Esposito, Massimo Iaculo, Eric Kwok Fung Yuen, Gerard J. Perdaems
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Patent number: 11169917Abstract: Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.Type: GrantFiled: January 14, 2020Date of Patent: November 9, 2021Assignee: Micron Technology, Inc.Inventors: Giuseppe D'Eliseo, Luigi Esposito, Xinghui Duan, Lucia Santojanni, Massimo Iaculo
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Patent number: 11106521Abstract: Devices and techniques for fatal error logging in a memory device are described herein. For example a read request can be received for a component of the memory device. A fatal error indication of an error that prevents correct execution of read request can be detected. Diagnostic information for the failure indication can be collected. A response to the read request can then be made with a portion of the diagnostic information as payload instead of the user data that would have occupied the payload had the read succeeded. Metadata in the response can be used to communicate an error code.Type: GrantFiled: August 19, 2019Date of Patent: August 31, 2021Assignee: Micron Technology, Inc.Inventors: Luigi Esposito, Paolo Papa, Massimo Iaculo, Erika Morvillo
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Patent number: 11100996Abstract: Devices and techniques for managing flash memory are disclosed herein. A memory controller may receive a first program request comprising first host data to be written to the flash memory. The flash memory may comprise a number of storage units with each storage unit comprising a number of storage sub-units. If the first host data is less than a remainder threshold, the memory controller may generate a first program data unit comprising the first host data and first log data describing the flash memory. The memory controller may program the program data unit to the first storage unit of the flash memory, where the first log data is written to a first storage sub-unit of the number of storage sub-unit. The memory controller may also store an indication that the first storage sub-unit is invalid.Type: GrantFiled: August 30, 2017Date of Patent: August 24, 2021Assignee: Micron Technology, Inc.Inventors: Paolo Papa, Luigi Esposito, Massimo Iaculo, Eric Kwok Fung Yuen, Gerard J. Perdaems
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Publication number: 20210240633Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.Type: ApplicationFiled: April 19, 2021Publication date: August 5, 2021Inventors: Carminantonio Manganelli, Yoav Weinberg, Alberto Sassara, Paolo Papa, Luigi Esposito, Giuseppe D'Eliseo, Angelo Della Monica, Massimo Iaculo
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Patent number: 10983918Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.Type: GrantFiled: March 6, 2019Date of Patent: April 20, 2021Assignee: Micron Technology, Inc.Inventors: Carminantonio Manganelli, Yoav Weinberg, Alberto Sassara, Paolo Papa, Luigi Esposito, Giuseppe D'Eliseo, Angelo Della Monica, Massimo Iaculo