Abstract: A calibration circuit may include a calibration signal generator configured to receive an oscillator signal provided by an oscillator and generate a calibration signal based on the oscillator signal. The calibration signal may be generated to have a predetermined amplitude. The calibration circuit may include a calibration peak detector configured to detect a peak amplitude of the calibration signal. The calibration circuit may include a logic circuit configured to calibrate a peak detector connected to the oscillator based at least in part on the peak amplitude of the calibration signal.

Abstract: A digital phase-locked loop (DPLL) may include a delta-sigma modulator (DSM). The DSM may include a delay component configured to perform noise shaping of a quantization error introduced by the DSM. The DSM may include a noise transfer function (NTF) component configured to perform filtering of the quantization error introduced by the DSM. The DSM may include an adjustment transfer function (ATF) component configured to cause the filtering of the quantization error to be applied on top of the noise shaping such that an impact of the NTF component on the noise shaping is reduced.

Abstract: A calibration circuit may include a calibration signal generator configured to receive an oscillator signal provided by an oscillator and generate a calibration signal based on the oscillator signal. The calibration signal may be generated to have a predetermined amplitude. The calibration circuit may include a calibration peak detector configured to detect a peak amplitude of the calibration signal. The calibration circuit may include a logic circuit configured to calibrate a peak detector connected to the oscillator based at least in part on the peak amplitude of the calibration signal.

Abstract: The disclosure relates to a circuit including a current mirror circuit with a current path including a first transistor and a replica current path including a second transistor. The current path is connected to the replica current path to influence a current in the replica current path based on a reference current in the current path. The current in the replica current path may be proportional to the reference current. The circuit further includes a capacitor coupled between a gate of the second transistor and a first potential, a switch coupled between a gate of the first transistor and the gate of the second transistor to selectively disconnect the gate of the first transistor from the gate of the second transistor and from a first electrode of the capacitor. The disclosure further relates to a method for operating a circuit including a current mirror circuit.

Abstract: A digital phase-locked loop (DPLL) may include a delta-sigma modulator (DSM). The DSM may include a delay component configured to perform noise shaping of a quantization error introduced by the DSM. The DSM may include a noise transfer function (NTF) component configured to perform filtering of the quantization error introduced by the DSM. The DSM may include an adjustment transfer function (ATF) component configured to cause the filtering of the quantization error to be applied on top of the noise shaping such that an impact of the NTF component on the noise shaping is reduced.

Abstract: A digital phase-locked loop (DPLL) circuit includes: a first time-to-digital converter (TDC) and a first digital loop filter (DLF) that are configured to be coupled between a reference clock source and a digitally controlled oscillator (DCO), where the first TDC is configured to, during an acquisition mode, generate a phase error by: receiving a reference clock signal from the reference clock source; receiving a clock signal that is based on an output of the DCO divided by a dividing factor, computing a phase error using the reference clock signal and the clock signal; detecting cycle slipping in the computed phase error; and in response to detecting the cycle slipping, modifying the computed phase error to reduce the impact of cycle slipping on the DPLL circuit; and a first frequency divider circuit configured to generate the clock signal by dividing the output of the DCO by the dividing factor.

Abstract: A method of applying digital pre-distortion includes: outputting, by a look-up table, a first table value based on an input digital signal; adding the first table value and the input digital signal to generate a first combined signal comprising a first combined value having a first integer coefficient and a first fractional coefficient; separating the first integer coefficient from the first fractional coefficient to generate a first integer signal representing the first integer coefficient and a first fractional signal representing the first fractional coefficient; generating a delta-sigma modulated signal based on the first fractional signal; converting, by a first digital-to-analog, a first digital signal into a first analog signal, wherein the first digital signal is representative of the first integer signal; and converting, by a second DAC, a second digital signal into a second analog signal, wherein the second digital signal is representative of the delta-sigma modulated signal.

Abstract: A method of applying digital pre-distortion includes: outputting, by a look-up table, a first table value based on an input digital signal; adding the first table value and the input digital signal to generate a first combined signal comprising a first combined value having a first integer coefficient and a first fractional coefficient; separating the first integer coefficient from the first fractional coefficient to generate a first integer signal representing the first integer coefficient and a first fractional signal representing the first fractional coefficient; generating a delta-sigma modulated signal based on the first fractional signal; converting, by a first digital-to-analog, a first digital signal into a first analog signal, wherein the first digital signal is representative of the first integer signal; and converting, by a second DAC, a second digital signal into a second analog signal, wherein the second digital signal is representative of the delta-sigma modulated signal.

Abstract: A dynamic element matching (DEM) encoder is provided that converts an N-bit digital codeword into a pattern of 1-bit values. The DEM encoder includes a binary switching tree that includes plurality of switching blocks interconnected between an encoder input and a plurality of encoder outputs. The plurality of switching blocks are configured to receive a plurality of first control signals such that each switching block receives a respective first control signal and is independently programmable based on the respective first control signal into a first mode or a second mode. Each switching block includes a splitting circuit programmed into the first mode or the second mode to split a digital input into two digital outputs using either both a first splitting operation and a second splitting operation that is different from the first splitting operation or the first splitting operation over the plurality of sampling intervals.

Abstract: A digital phase-locked loop (DPLL) may include a time-to-digital converter (TDC) to provide a phase error signal, a frequency-divider to perform frequency division on an output signal to generate a frequency-divided output signal, a delta-sigma-modulator (DSM) to provide a test signal that represents a quantization error of the DSM, and a digital-to-time converter (DTC) to at least partially remove the quantization error from the frequency-divided output signal based on the test signal to generate the feedback signal. The DPLL may include a circuit to cause the DTC to provide a percentage of the quantization error such that the percentage of the quantization error is in the phase error signal, and a TDC calibration component to calibrate the TDC by applying a gain adjustment factor to the TDC. The gain adjustment factor may be based on the test signal and the phase error signal including the percentage of the quantization error.

Abstract: In accordance with an embodiment, a method of operating a fractional-N phase locked loop (FN-PLL) includes: dividing a first clock signal using a multi-modulus divider (MMD) based on a modulus control signal to form a frequency-divided clock signal, where the first clock signal is based on an output clock of the PLL; generating the modulus control signal based on a divider control input value using a delta-sigma modulator (DSM); and when a fractional portion of the divider control input value is within a first range of values, and repeatedly removing a first number of clock cycles from the first clock signal before dividing the first clock signal using the MMD, where the first number of clock cycles is a non-integer number of clock cycles.

Abstract: An oscillator includes: a first inductor; and a programmable capacitor bank coupled between a first terminal of the first inductor and a second terminal of the first inductor, where the programmable capacitor bank includes a plurality of cells concatenated together, where each cell of the plurality of cells includes a first node, a second node, a third node, a second inductor, and a programmable capacitor, where the second inductor is coupled between the first node and the third node, and the programmable capacitor is coupled between the third node and the second node, where a first inductance of the first inductor is larger than a sum of the inductances of the second inductors of the programmable capacitor bank.

Abstract: A method of operating a phase-locked loop (PLL) having a dynamic element matching (DEM)-driven digitally controlled oscillator (DCO) includes calibrating the PLL, where calibrating the PLL includes opening a loop of the PLL and performing linearity measurements of the DEM-driven DCO when the loop of the PLL is open and when dynamic matching of the DEM-driven DCO is activated, where performing the linearity measurements includes: applying test control words to the DEM-driven DCO to obtain frequencies in a first range of frequencies; and measuring output frequencies of the DEM-driven DCO corresponding to the test control words. Calibrating the PLL further includes calculating calibration information based on the test control words and the measured output frequencies.

Abstract: In accordance with an embodiment, a ring oscillator includes a plurality of stages coupled in a ring configuration, where stage of the plurality of stages has an input node coupled to an output node of a previous stage of the plurality of stages. Each stage of the plurality of stages includes: a ring oscillator transistor having a control node coupled to the input node, and a load path coupled to the output node; a direct injection circuit having a load path coupled between the control node of the ring oscillator transistor and the output node, and a control node coupled to a first oscillator input node; and a tail injection circuit having a load path coupled between the output node and a first power supply node, and a control node coupled to a second oscillator input node.

Abstract: The present invention. The invention relates to the use of interferon-? (IFN-?) for treating and/or preventing Alzheimer's disease (AD), Creutzfeld-Jakob disease (CJD) or Gerstmann-Sträussler-Scheinker disease (GSSD). It further relates to the use of IFN-? in combination with an Alzheimer's disease treating agent for treating and/or preventing Alzheimer's disease. The use of IFN-? in combination with a cholinesterase inhibitor for treating and/or preventing early-onset Alzheimer's disease is preferred.

Abstract: A machine for the therapeutic treatment of lumbago and lumbago-sciatica comprising a fixed footplate and a footplate movable angularly as a result of the weight of the patient supported in an upright position with one foot on one footplate and another foot on the other footplate with the footplates arranged one in front of the other so that the patient is supported by them in a substantially ambulatory positions with the movable footplate having two adjacent portions intended to act as a support for the front part of the foot and for the heel, respectively. Both portions of the movable footplate are connected to a balanced counterweight designed to maintain the portions in a plurality of prefixed equilibrium positions and in such a way that an angular displacement of one of the positions results in a corresponding opposite angular displacement of the other portion.