Abstract: A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.

Abstract: A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.

Abstract: A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.

Abstract: A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.

Abstract: A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.

Abstract: A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.

Abstract: Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of the first conductive strip, and an insulation region arranged between the first conductive strip and the control gate region. The first conductive strip includes a conduction line having a first conductivity type and a control line having a second conductivity type, arranged adjacent and in electrical contact with each other, and the conduction line forms the channel portion, a first conduction portion and a second conduction portion arranged on opposite sides of the channel portion.

Abstract: A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.

Abstract: Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of the first conductive strip, and an insulation region arranged between the first conductive strip and the control gate region. The first conductive strip includes a conduction line having a first conductivity type and a control line having a second conductivity type, arranged adjacent and in electrical contact with each other, and the conduction line forms the channel portion, a first conduction portion and a second conduction portion arranged on opposite sides of the channel portion.

Abstract: A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.

Abstract: Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of the first conductive strip, and an insulation region arranged between the first conductive strip and the control gate region. The first conductive strip includes a conduction line having a first conductivity type and a control line having a second conductivity type, arranged adjacent and in electrical contact with each other, and the conduction line forms the channel portion, a first conduction portion and a second conduction portion arranged on opposite sides of the channel portion.

Abstract: A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.

Abstract: A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.

Abstract: A configuration terminal for integrated devices includes a first and a second portion structurally independent and connected to respective first and second terminals and it has at least one contact terminal suitable to be selectively connected to such first and second terminals. Also a method configures an integrated device that includes a plurality of address pads and respective supply pins. The method includes: realizing at least one configuration terminal having a first and a second portion structurally independent and connected to at least one contact terminal; providing the contact of such first and second portions with respective terminals; and configuring the device by a short-circuiting of the contact terminal with at least one of said terminals.

Abstract: Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of the first conductive strip, and an insulation region arranged between the first conductive strip and the control gate region. The first conductive strip includes a conduction line having a first conductivity type and a control line having a second conductivity type, arranged adjacent and in electrical contact with each other, and the conduction line forms the channel portion, a first conduction portion and a second conduction portion arranged on opposite sides of the channel portion.

Abstract: A method for accessing, in reading, programming, and erasing a semiconductor-integrated non-volatile memory device of the Flash EEPROM type with a NAND architecture having at least one memory matrix organized in rows or word lines and columns or bit lines, and wherein, for the memory, a plurality of additional address pins are provided. The method provides both an access protocol of the asynchronous type and a protocol of the extended type allowing to address, directly and in parallel, a memory extended portion by loading an address register associated with the additional pins in two successive clock pulses. A third multi-sequential access mode and a parallel additional bus referring to the additional address pins are also provided to allow a double addressing mode, sequential and in parallel.

Abstract: A configuration terminal for integrated devices includes a first and a second portion structurally independent and connected to respective first and second terminals and it has at least one contact terminal suitable to be selectively connected to such first and second terminals. Also a method configures an integrated device that includes a plurality of address pads and respective supply pins. The method includes: realizing at least one configuration terminal having a first and a second portion structurally independent and connected to at least one contact terminal; providing the contact of such first and second portions with respective terminals; and configuring the device by a short-circuiting of the contact terminal with at least one of said terminals.

Abstract: A method for accessing, in reading, programming, and erasing a semiconductor-integrated non-volatile memory device of the Flash EEPROM type with a NAND architecture having at least one memory matrix organized in rows or word lines and columns or bit lines, and wherein, for the memory, a plurality of additional address pins are provided. The method provides both an access protocol of the asynchronous type and a protocol of the extended type allowing to address, directly and in parallel, a memory extended portion by loading an address register associated with the additional pins in two successive clock pulses. A third multi-sequential access mode and a parallel additional bus referring to the additional address pins are also provided to allow a double addressing mode, sequential and in parallel.

Abstract: A method for accessing, in reading, programming, and erasing a semiconductor-integrated non-volatile memory device of the Flash EEPROM type with a NAND architecture having at least one memory matrix organized in rows or word lines and columns or bit lines, and wherein, for the memory, a plurality of additional address pins are provided. The method provides both an access protocol of the asynchronous type and a protocol of the extended type allowing to address, directly and in parallel, a memory extended portion by loading an address register associated with the additional pins in two successive clock pulses. A third multi-sequential access mode and a parallel additional bus referring to the additional address pins are also provided to allow a double addressing mode, sequential and in parallel.

Abstract: A row decoder circuit is described of the type comprising at least one input stage connected to a first supply voltage reference and to an output stage connected to a second supply voltage reference, the output stage having at least one output terminal connected to a word line of a memory matrix. The row decoder circuit further comprises a biasing device, connected to a third supply voltage reference and comprising at least one generator of a negative voltage connected to a divider, in turn connected to a first biasing terminal of the biasing device. In particular, the first biasing terminal is connected to at least one input stage in correspondence with bulk terminals of MOS transistors comprised in the input stage and it is suitable for supplying it with a first negative voltage.