Abstract: A d-c/d-c converter has two switching transistors connected in push-pull across respective primary halves of an output transformer working into a full-wave rectifier, these primary halves lying in parallel with the primary of a self-saturating feedback transformer whose secondary is split into halves respectively inserted in the emitter/base circuits of the two transistors. The primary of the feedback transformer is shunted by a protective network which comprises a capacitor in series with a rectifier bridge; the network may also include one or two thyristors fired in response to an excessive collector current drawn by the transistors.

Abstract: A load, such as a logic network of the TTL type, is connected in parallel across a plurality of direct-current sources designed to maintain a substantially constant operating voltage. Each source includes a control unit which compares the load voltage with a reference level in order to stabilize the output voltage of an associated current generator at that level. If the generator current drops below a certain minimum value, however, a threshold sensor in the control unit raises the reference level up to an amount equaling about twice the maximum divergence possible between the reference levels of different control units, thereby ensuring that all sources contribute simultaneously to the load current.

Abstract: A self-balancing d-c/a-c converter comprises a transformer whose primary winding is split into a pair of symmetrical halves each connected in series with a respective transistor and an associated resistor across a supply of direct current. A differential amplifier, with inputs connected across the two resistors through a pair of low-pass filters, generates an unbalance signal d in the form of a voltage of either polarity which is additively and subtractively superimposed upon a reference voltage e to provide two control signals e+d and e-d fed to respective inputs of two comparators. Two synchronized signal generators produce a sawtooth oscillation a and a square wave f, the latter having a period which is twice that of the former. Sawtooth wave a is fed in parallel to the other inputs of the two comparators while the square wave f and its complement g alternately unblock a pair of AND gates in cascade with these comparators.