Abstract: It is disclosed a method for updating a cumulative residence time of a synchronization packet received at a node of a packet-switched communication network. The cumulative residence time is equal to a cumulative sum of residence times of the packet at nodes interposed between a further node which has generated the packet and the node. The node comprises an ingress circuit and an egress circuit. The method comprises: receiving the packet at the egress circuit from the ingress circuit; at a timestamp generator of the egress circuit, generating a timestamp; at the egress circuit, calculating a virtual timestamp based on the timestamp and on an estimated variable delay that will be undergone by the packet due to buffering in a buffer located downstream the timestamp generator; and, at the egress circuit, using the virtual timestamp for updating the cumulative residence time, before transmitting the packet to a still further node.

Abstract: A network element for a digital transmission network is proposed. The network element contains two switching matrices for switching data cells, as well as ingress ports that receive TDM traffic flow and packet traffic flow and segment the traffic flows into cells. A control system for controlling the configuration of the ingress ports and the switching matrices controls the ingress ports, in case of no failure of the switching matrices, to forward the TDM traffic flows to both switching matrices and to split the packet traffic flow over the two switching matrices.

Abstract: There is described a method for transmitting N parallel data flows on a parallel bus. The method comprises, at a first communication device: generating a further parallel data flow comprising alignment words periodically distributed with a period; at each period, rotating the N of parallel data flows and the further parallel data flow thus generating N+1 rotated parallel data flows, each comprising part of the alignment words periodically distributed with a frame period; transmitting the N+1 rotated parallel data flows on respective physical connections of the parallel bus. The method further comprises, at a second communication device: aligning the N+1 rotated parallel data flows by using the alignment words, thus compensating skew and obtaining N+1 aligned parallel data flows; and at each period, de-rotating the N+1 aligned parallel data flows, thus generating N de-rotated parallel data flows corresponding to the N parallel data flows.

Abstract: A network element for a digital transmission network is proposed. The network element contains two switching matrices for switching data cells, as well as ingress ports that receive TDM traffic flow and packet traffic flow and segment the traffic flows into cells. A control system for controlling the configuration of the ingress ports and the switching matrices controls the ingress ports, in case of no failure of the switching matrices, to forward the TDM traffic flows to both switching matrices and to split the packet traffic flow over the two switching matrices.

Abstract: Equipment protection of a switch matrix (SM) in a network node, which contains a number of matrix modules (M1.1-M4.4, E1.5-E4.6) is achieved by slicing an input signal into k parallel signal slices (x(0)-x(3)) with k>2; coding the k signal slices into a number of n coded signal slices (x(0)-x(5)) with n>k+1 using an error correcting code to add redundancy to said input signal; switching said n coded signal slices through the switching matrix (SM) via n distinct matrix modules; and decoding the n coded signal slices into k decoded signal slices to correct errors introduced while passing through said switch matrix. Preferably, the switch matrix (SM) contains a first number of matrix boards (MB1-MB4, EB5, EB6), each carrying a second number of matrix modules (M1.1-M4.4, E1.5-E4.6). The n coded signal slices are switched via matrix modules on n distinct matrix boards.

Abstract: It is disclosed a method for updating a cumulative residence time of a synchronization packet received at a node of a packet-switched communication network. The cumulative residence time is equal to a cumulative sum of residence times of the packet at nodes interposed between a further node which has generated the packet and the node. The node comprises an ingress circuit and an egress circuit. The method comprises: receiving the packet at the egress circuit from the ingress circuit; at a timestamp generator of the egress circuit, generating a timestamp; at the egress circuit, calculating a virtual timestamp based on the timestamp and on an estimated variable delay that will be undergone by the packet due to buffering in a buffer located downstream the timestamp generator; and, at the egress circuit, using the virtual timestamp for updating the cumulative residence time, before transmitting the packet to a still further node.

Abstract: There is described a method for transmitting N parallel data flows on a parallel bus. The method comprises, at a first communication device: generating a further parallel data flow comprising alignment words periodically distributed with a period; at each period, rotating the N of parallel data flows and the further parallel data flow thus generating N+1 rotated parallel data flows, each comprising part of the alignment words periodically distributed with a frame period; transmitting the N+1 rotated parallel data flows on respective physical connections of the parallel bus. The method further comprises, at a second communication device: aligning the N+1 rotated parallel data flows by using the alignment words, thus compensating skew and obtaining N+1 aligned parallel data flows; and at each period, de-rotating the N+1 aligned parallel data flows, thus generating N de-rotated parallel data flows corresponding to the N parallel data flows.

Abstract: Equipment protection of a switch matrix (SM) in a network node, which contains a number of matrix modules (M1.1-M4.4, E1.5-E4.6) is achieved by slicing an input signal into k parallel signal slices (x(0)-x(3)) with k>2; coding the k signal slices into a number of n coded signal slices (x(0)-x(5)) with n>k+1 using an error correcting code to add redundancy to said input signal; switching said n coded signal slices through the switching matrix (SM) via n distinct matrix modules; and decoding the n coded signal slices into k decoded signal slices to correct errors introduced while passing through said switch matrix. Preferably, the switch matrix (SM) contains a first number of matrix boards (MB1-MB4, EB5, EB6), each carrying a second number of matrix modules (M1.1-M4.4, E1.5-E4.6). The n coded signal slices are switched via matrix modules on n distinct matrix boards.

Abstract: It is disclosed a method for decoding an information word from a set of coded words. The method comprises the steps of receiving a coded word, of selecting a coded word having the minimum distance from the received coded word from a pre-configured sub-set of the set of the coded words, wherein the sub-set is configured to at least two coded words having each other a distance higher than the minimum distance between the coded words of the set, and of decoding the information word from the selected coded word.

Abstract: A method and apparatus for interfacing a parallel connection, the parallel connection transmitting high bit-rate signals for a short distance. The method comprises: receiving a synchronous N-bits input data flow at a first input frequency; inserting said input data flow into parallel packets having a given length; and outputting said packets having a given length at a second output frequency onto a M-wires parallel connection.

Abstract: A packet pipe architecture is disclosed for an access network (e.g., provides access to an IP, ATM or similar packet-based network in order to convey packet data traffic), whereby the network interfaces with the packet pipe are standardized so that any packet pipe that satisfies the interface requirements can be utilized in the same access network. Also, the packet pipe uses a packet-based protocol stack with Quality of Service provisions for service delivery instead of the conventional best effort service delivery functions used. Consequently, the packet pipe and access network are capable of providing all of the numerous services available with an IP, ATM or similar packet-based network layered architecture.

Abstract: A packet pipe architecture for an access network (e.g., provides access to an IP, ATM or similar packet-based network in order to convey packet data traffic), whereby the network interfaces with the packet pipe are standardized so that any packet pipe that satisfies the interface requirements can be utilized in the same access network. Also, the packet pipe uses a packet-based protocol stack with Quality of Service provisions for service delivery instead of the conventional best effort service delivery functions used. Consequently, the packet pipe and access network are capable of providing all of the numerous services available with an IP, ATM or similar packet-based network layered architecture.

Abstract: A method and apparatus for interfacing a parallel connection, the parallel connection transmitting high bit-rate signals for a short distance. The method comprises: receiving a synchronous N-bits input data flow at a first input frequency; inserting said input data flow into parallel packets having a given length; and outputting said packets having a given length at a second output frequency onto a M-wires parallel connection.

Abstract: A system for controlling the rate of flow of data generated by a variable rate data source and fed to a buffer which outputs the data at a constant bit rate. The operating mode, which sets the bit rate of the variable rate data source, is determined not only by the degree to which the buffer is filled, but also by the immediately preceding operating mode. The feedback of the operating mode results in an hysteresis effect on the mode, thus reducing the number of changes of the rate of data generation and thereby increasing the transmission quality of the data generated and output from the system.

Abstract: A method for reducing the information transmitted in the variable length encoding of numerical data blocks with encoding of single values and string lengths of a consecutive value ("run lengths"). Advantageously, the system eliminates that transmission of the last element in a string of recurrent values preceded by a "run length" and followed by another "run length" or by a data block end. When the string of recurrent values has a length of only one element, the single element is not transmitted.

Abstract: A converter processes a digital video signal according to a known redundancy reducing algorithm executed on successive block for each frame or field and generates a transformed signal which is applied to a quantizer adapted to generate a quantized signal at preset transition levels on opposed sides of the zero, including the zero ( . . . ,-3,-2,-1, 0, 1, 2, 3, . . . ). The quantized signal is processed by a processor, adapted to determine the block length and the consecutive zero sequences along a preset scanning order, and to output a symbolic signal constituted by symbols indicating the quantization levels of the non-null data, the zero sequences and a symbol indicating the block end. The symbolic signal is applied to a variable length VLC encoder, adapted to encode data according to a preset designation law for generating a signal which is applied to a transmission buffer.

Abstract: The digital signal is decomposed in intrafield blocks each comprising a set number of adjacent image elements, and each intrafield block, or an intrafield block or an interframe block derived therein, is subjected to a Discrete Cosine Transform and the transformed signal is applied to quantizer to generate a quantized signal which is encoded at variable length and loaded to a transmission buffer, the quantization resolution being inversely proportional to the buffer fill rate. According to the invention, a digital low-pass filter is connected to filter the block to be subjected to Discrete Cosine Transform, and is subjected to the buffer so that its upper-frequency cutoff lowers as the buffer fill rate increases.