Patents by Inventor Luis A. Huertas-Sanchez

Luis A. Huertas-Sanchez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and apparatus for driver circuit for protection of gates of GaN FETs
    Patent number: 8593211
    Abstract: A half-bridge power circuit comprises a first gallium nitride field effect transistor (GaN FET); a first driver coupled to a gate of the first GaN FET; an anode of a capacitor coupled to an output of the driver and a source of the first GaN FET; a diode having a cathode coupled to the cathode of the capacitor; and a bootstrap capacitor clamp (BCC) controller, including: a field effect transistor (FET) coupled to an anode of the diode, and a comparator coupled to a gate of the FET, the comparator configured to receive as inputs: a) a signal representative of an input voltage (VDRV) applied to the FET; b) a ground; c) a boot signal representative of a voltage at the anode of the capacitor (Boot); and d) a signal representative of a voltage at the source of the first GaN FET (SW).
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: November 26, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Hassan Pooya Forghani-Zadeh, Luis A. Huertas-Sanchez
  • System and Apparatus for Driver Circuit for Protection of Gates of GaN FETs
    Publication number: 20130241621
    Abstract: A half-bridge power circuit comprises a first gallium nitride field effect transistor (GaN FET); a first driver coupled to a gate of the first GaN FET; an anode of a capacitor coupled to an output of the driver and a source of the first GaN FET; a diode having a cathode coupled to the cathode of the capacitor; and a bootstrap capacitor clamp (BCC) controller, including: a field effect transistor (FET) coupled to an anode of the diode, and a comparator coupled to a gate of the FET, the comparator configured to receive as inputs: a) a signal representative of an input voltage (VDRV) applied to the FET; b) a ground; c) a boot signal representative of a voltage at the anode of the capacitor (Boot); and d) a signal representative of a voltage at the source of the first GaN FET (SW).
    Type: Application
    Filed: March 16, 2012
    Publication date: September 19, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hassan Pooya Forghani-Zadeh, Luis A. Huertas-Sanchez
  • DYING GASP CHARGE CONTROLLER
    Publication number: 20110109374
    Abstract: In many applications, “dying gasp” periods following power down are used. Conventional circuits supply energy for the “dying gasp” periods generally by use of large external capacitors that are bulky and expensive. Here, a dying gasp charge controller is employed that allows for the use of smaller capacitors at higher voltages, which maintains or exceeds the energy storage capacities of conventional circuits.
    Type: Application
    Filed: November 11, 2009
    Publication date: May 12, 2011
    Applicant: Texas Instruments Incorporated
    Inventors: Hassan Pooya Forghani-zadeh, Luis A. Huertas-Sanchez, Li Li
  • Dying gasp charge controller
    Patent number: 7940118
    Abstract: In many applications, “dying gasp” periods following power down are used. Conventional circuits supply energy for the “dying gasp” periods generally by use of large external capacitors that are bulky and expensive. Here, a dying gasp charge controller is employed that allows for the use of smaller capacitors at higher voltages, which maintains or exceeds the energy storage capacities of conventional circuits.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: May 10, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Hassan Pooya Forghani-zadeh, Luis A. Huertas-Sanchez, Li Li