Abstract: The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the embedded core. A test wrapper including boundary scan test (BST) cells may be used to test an embedded core. Dual function BST/ATPG (Automatic Test Pattern Generation) cells may be used to perform both BST and ATPG tests on embedded cores. A BIST (Built-In Self Test) controller supporting a “resume” mode in addition to a “pass/fail” mode may be used to compensate for timing latencies introduced by pipeline staging in an embedded memory array.