Abstract: Neural networks can be implemented with DNA strand displacement (DSD) circuits. The neural networks are designed and trained in silico taking into account the behavior of DSD circuits. Oligonucleotides comprising DSD circuits are synthesized and combined to form a neural network. In an implementation, the neural network may be a binary neural network in which the output from each neuron is a binary value and the weight of each neuron either maintains the incoming binary value or flips the binary value. Inputs to the neural network are one more oligonucleotides such as synthetic oligonucleotides containing digital data or natural oligonucleotides such as mRNA. Outputs from the neural networks may be oligonucleotides that are read by directly sequencing or oligonucleotides that generate signals such as by release of fluorescent reporters.

Abstract: Examples of systems and methods described herein may provide saliency-based video compression. A saliency map associated with a video may be generated and/or provided. A tile configuration may be selected for the video and quality settings assigned to each tile in accordance with the saliency map. The video may then be compressed (e.g., encoded) in tiles in accordance with the quality settings. Compressed videos may be stored together with saliency metadata, facilitating storage management and/or re-compression.

Abstract: Neural networks can be implemented with DNA strand displacement (DSD) circuits. The neural networks are designed and trained in silico taking into account the behavior of DSD circuits. Oligonucleotides comprising DSD circuits are synthesized and combined to form a neural network. In an implementation, the neural network may be a binary neural network in which the output from each neuron is a binary value and the weight of each neuron either maintains the incoming binary value or flips the binary value. Inputs to the neural network are one more oligonucleotides such as synthetic oligonucleotides containing digital data or natural oligonucleotides such as mRNA. Outputs from the neural networks may be oligonucleotides that are read by directly sequencing or oligonucleotides that generate signals such as by release of fluorescent reporters.

Abstract: In some embodiments, techniques are provided for conducting similarity-based searches using DNA. In some embodiments, sets of features that represent stored data sets are encoded in DNA sequences such that a hybridization yield between a molecule having a given stored DNA sequence and a molecule having a reverse complement of a DNA sequence that encodes a set of features that represent a query data set reflects an amount of similarity between the set of features that represent the query data set and the set of features encoded in the given stored DNA sequence. In some embodiments, machine learning techniques are used to determine the DNA sequence encoding. In some embodiments, machine learning techniques are used to predict hybridization yields between DNA molecules.

Abstract: Examples of systems and methods described herein may provide saliency-based video compression. A saliency map associated with a video may be generated and/or provided. A tile configuration may be selected for the video and quality settings assigned to each tile in accordance with the saliency map. The video may then be compressed (e.g., encoded) in tiles in accordance with the quality settings. Compressed videos may be stored together with saliency metadata, facilitating storage management and/or re-compression.

Abstract: Artificial polynucleotides may have different characteristics than natural polynucleotides so conventional base-calling algorithms may make incorrect base calls. However, because artificial polynucleotides are typically designed to have certain characteristics, the known characteristics of the artificial polynucleotide can be used to modify the base-calling algorithm. This disclosure describes polynucleotide sequencers adapted to sequence artificial polynucleotides by modifying a base-calling algorithm of the polynucleotide sequencer according to known characteristics of the artificial polynucleotides. The base-calling algorithm analyzes raw data generated by a polynucleotide sequencer and identifies which nucleotide base occupies a given position on a polynucleotide strand.

Abstract: A technique for clustering DNA reads from polynucleotide sequencing is described. DNA reads with a level of difference that is likely caused by errors in sequencing are grouped together in the same cluster. DNA reads that represent reads of different DNA molecules are placed in different clusters. The clusters are based on edit distance, which is the number of changes necessary to convert a given DNA read into another. The process of forming clusters may be performed iteratively and may use other types of distance that serve as an approximation for edit distance. Well clustered DNA reads provide a starting point for further analysis.

Abstract: Neural networks can be implemented with DNA strand displacement (DSD) circuits. The neural networks are designed and trained in silico taking into account the behavior of DSD circuits. Oligonucleotides comprising DSD circuits are synthesized and combined to form a neural network. In an implementation, the neural network may be a binary neural network in which the output from each neuron is a binary value and the weight of each neuron either maintains the incoming binary value or flips the binary value. Inputs to the neural network are one more oligonucleotides such as synthetic oligonucleotides containing digital data or natural oligonucleotides such as mRNA. Outputs from the neural networks may be oligonucleotides that are read by directly sequencing or oligonucleotides that generate signals such as by release of fluorescent reporters.

Abstract: Artificial polynucleotides may have different characteristics than natural polynucleotides so conventional base-calling algorithms may make incorrect base calls. However, because artificial polynucleotides are typically designed to have certain characteristics, the known characteristics of the artificial polynucleotide can be used to modify the base-calling algorithm. This disclosure describes polynucleotide sequencers adapted to sequence artificial polynucleotides by modifying a base-calling algorithm of the polynucleotide sequencer according to known characteristics of the artificial polynucleotides. The base-calling algorithm analyzes raw data generated by a polynucleotide sequencer and identifies which nucleotide base occupies a given position on a polynucleotide strand.

Abstract: Polynucleotide sequencing generates multiple reads of a polynucleotide molecule. Many or all of the reads may contain errors. Trace reconstruction takes multiple reads generated by a polynucleotide sequencer and uses those multiple reads to reconstruct accurately the nucleotide sequence. The types of errors are substitutions, deletions, and insertions. The location of an error in a read is identified by comparing the sequence of the read to the other reads. The type of error is determined by comparing both the base call of the read at the error location and base calls of the read and other reads in a look-ahead window that includes base calls adjacent to the error location. A consensus output sequence is developed from the sequences of the multiple reads and identification of the error types for errors in the reads.

Abstract: Methods, servers, and systems for using signatures/certifications embedded in pre-processed code to enable use or reuse of pre-processed code to obviate the need to perform some operations or execute some scripts within the web page content. One or more operations may be performed within an executable script in web page content and signing the result of the operation in a manner that can be used to verify that the corresponding operation may be skipped by a browser. A browser receiving signed pre-processed code may use a signature verification process to determine whether the browser can bypass executing corresponding scripts in the web page content or perform alternative operations. Operations may be pre-performed and the results signed by off-line tools and included in the web page content. Results of operations may be stored in memory along with a signature so the results of the operation can be reused in the future.

Abstract: Devices and methods of providing hardware support for dynamic type checking are provided. In some embodiments, a processor includes a type check register and support for one or more checked load instructions. In some embodiments, normal load instructions are replaced by a compiler with the checked load instructions. In some embodiments, to perform a checked load, an error handler instruction location is stored in the type check register, and a type tag operand is compared to a type tag stored in the loaded memory location. If the comparison succeeds, execution may proceed normally. If the comparison fails, execution may be transferred to the error handler instruction. In some embodiments, type prediction is performed to determine whether a checked load instruction is likely to fail.

Abstract: Methods and devices for accelerating webpage rendering by a browser store document object model (DOM) tree structures and computations of rendered pages, and compare portions of a DOM tree of pages being render to determining if portions of the DOM tree structures match. If a DOM tree of a webpage to be rendered matches a DOM tree stored in memory, the computations associated with the match DOM tree may be recalled from memory, obviating the need to perform the calculations to render the page. A tree isomorphism algorithm may be used to recognize DOM trees stored in memory that match the DOM tree of the webpage to be rendered. Reusing rendering computations may significantly reducing the time and resources required for rendering web pages. Identifying reusable portions of calculation results based on DOM tree isomorphism enables the browser to reuse stored webpage rendering calculations even when URLs do not match.

Abstract: Systems and methods for detecting concurrency bugs are provided. In some embodiments, context-aware communication graphs that represent inter-thread communication are collected during test runs, and may be labeled according to whether the test run was correct or failed. Graph edges that are likely to be associated with failed behavior are determined, and probable reconstructions of failed behavior are constructed to assist in debugging. In some embodiments, software instrumentation is used to collect the communication graphs. In some embodiments, hardware configured to collect the communication graphs is provided.

Abstract: The aspects enable a computing device to execute traditionally software-based JavaScript® operations in hardware. Each JavaScript® object is hashed into a master hashtable that may be stored in the software. A portion of the software hashtable may be pushed to a hardware hashtable using special instruction set registers dedicated to hashtable processing. Each time a software process requests a hashtable operation (e.g., lookup) the hardware hashtable is checked to determine if the value exists in hardware. If the requested value is in the hardware hashtable, the requested value is accessed in a single operation step. If the requested value is not in the hardware hashtable, the requested value is extracted from the master hashtable in the software and a portion of the master hashtable containing the extracted value is pushed to the hardware using special instruction set registers.

Abstract: Systems and methods for detecting concurrency bugs are provided. In some embodiments, context-aware communication graphs that represent inter-thread communication are collected during test runs, and may be labeled according to whether the test run was correct or failed. Graph edges that are likely to be associated with failed behavior are determined, and probable reconstructions of failed behavior are constructed to assist in debugging. In some embodiments, software instrumentation is used to collect the communication graphs. In some embodiments, hardware configured to collect the communication graphs is provided.

Abstract: Systems and methods for detecting concurrency bugs are provided. In some embodiments, context-aware communication graphs that represent inter-thread communication are collected during test runs, and may be labeled according to whether the test run was correct or failed. Graph edges that are likely to be associated with failed behavior are determined, and probable reconstructions of failed behavior are constructed to assist in debugging. In some embodiments, software instrumentation is used to collect the communication graphs. In some embodiments, hardware configured to collect the communication graphs is provided.

Abstract: A computer-implemented method for providing software fault tolerance is provided. A multithreaded program is executed. The program execution includes a plurality of multithreaded processes. A set of inputs is provided to one of the multithreaded processes and the inputs set is copied to each of the other multithreaded processes. The executions of the multithreaded processes are divided into deterministic subsets of the execution that end at a checkpoint. An execution of the deterministic subset is speculatively executed continuously on one of the multithreaded processes. Upon completion of execution through the checkpoint, the successfully completed execution path through the deterministic subset is retired. Execution of the deterministic instructions subset on the other multithreaded process is continued along the completed execution path.

Abstract: A hardware and/or software facility for controlling the order of operations performed by threads of a multithreaded application on a multiprocessing system is provided. The facility may serialize or selectively-serialize execution of the multithreaded application such that, given the same input to the multithreaded application, the multiprocessing system deterministically interleaves operations, thereby producing the same output each time the multithreaded application is executed. The facility divides the execution of the multithreaded application code into two or more quantum specifying a deterministic number of operations, and the facility specifies a deterministic order in which the threads execute the two or more quantum. The deterministic number of operations may be adapted to follow the critical path of the multithreaded application. Specified memory operations may be executed regardless of the deterministic order, such as those accessing provably local data.

Abstract: A computing system for scalable computing on commodity hardware is provided. The computing system includes a first computing device communicatively connected to a second computing device. The first computing device includes a processor, a physical computer-readable medium, and program instructions stored on the physical computer-readable medium and executable by the processor to perform functions. The functions include determining a first task associated with the second computing device and a second task associated with the second computing device are to be executed, assigning execution of the first task and the second task to the processor of the first computing device, generating an aggregated message that includes (i) a first message including an indication corresponding to the execution of the first task and (ii) a second message including an indication corresponding to the execution of the second task, and sending the aggregated message to the second computing device.