Abstract: The present invention relates to a compound represented by the following Formula (I) or a pharmaceutically acceptable salt thereof: wherein in Formula (I), definitions of R1, R2, L, m, and n are each shown in the specification.

Abstract: An apparatus, including: a buffer configured to receive an input differential signal and generate an output signal based on the input differential signal, wherein the buffer includes a first buffer stage including: a first field effect transistor (FET); a second FET coupled in series with the first FET between a first voltage rail and a second voltage rail; a third FET; a fourth FET coupled in series with the third FET between the first voltage rail and the second voltage rail, wherein the first and third FETs include gates coupled together, and wherein the second and fourth FETs include gates configured to receive positive and negative components of the input differential signal; and a first capacitor coupled between a drain of the second FET and the gates of the first and third FETs.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for minimizing, or at least reducing, a bias noise contribution to phase noise in an oscillator circuit. One example oscillator circuit generally includes an oscillator configured to generate an oscillating signal, an adjustable bias circuit coupled to a bias input of the oscillator and configured to provide a bias signal to the oscillator, and a control circuit having an input coupled to an output of the oscillator and having an output coupled to a control input of the adjustable bias circuit. The control circuit is configured to control the adjustable bias circuit to adjust the bias signal with a control signal, to determine an impact of the adjusted bias signal on a parameter of the oscillating signal, and to determine a setting for the control signal based on the impact on the parameter of the oscillating signal.

Abstract: An apparatus, including: a buffer configured to receive an input differential signal and generate an output signal based on the input differential signal, wherein the buffer includes a first buffer stage including: a first field effect transistor (FET); a second FET coupled in series with the first FET between a first voltage rail and a second voltage rail; a third FET; a fourth FET coupled in series with the third FET between the first voltage rail and the second voltage rail, wherein the first and third FETs include gates coupled together, and wherein the second and fourth FETs include gates configured to receive positive and negative components of the input differential signal; and a first capacitor coupled between a drain of the second FET and the gates of the first and third FETs.

Abstract: An IC includes a first set of MOS transistors configured to have a common first transistor source/drain terminal A, a first transistor gate, and a first transistor source/drain terminal B. In addition, the IC includes a first plurality of interconnect stacks coupled to the first transistor source/drain terminal A. Each interconnect stack of the first plurality of interconnect stacks extends in a second direction over at least a portion of the first set of MOS transistors and includes consecutive metal layer interconnects. Further, the IC includes a first comb interconnect structure extending in a first direction orthogonal to the second direction, with comb fingers extending in the second direction over at least a portion of the first set of MOS transistors and the first plurality of interconnect stacks. The first comb interconnect structure is coupled to the first plurality of interconnect stacks.

Abstract: A chip includes a first net, and a second net, wherein the first net and the second net are formed from a same metal layer, and the second net neighbors the first net. The chip also includes first vias disposed on the first net, and second vias disposed on the second net. A first spacing is greater than a second spacing, the first spacing is between a first one of the first vias and a second one of the first vias, the first one of the first vias and the second one of the first vias are adjacent, and the second spacing is between the first one of the first vias and one of the second vias closest to the first one of the first vias.

Abstract: An IC includes a first set of MOS transistors configured to have a common first transistor source/drain terminal A, a first transistor gate, and a first transistor source/drain terminal B. In addition, the IC includes a first plurality of interconnect stacks coupled to the first transistor source/drain terminal A. Each interconnect stack of the first plurality of interconnect stacks extends in a second direction over at least a portion of the first set of MOS transistors and includes consecutive metal layer interconnects. Further, the IC includes a first comb interconnect structure extending in a first direction orthogonal to the second direction, with comb fingers extending in the second direction over at least a portion of the first set of MOS transistors and the first plurality of interconnect stacks. The first comb interconnect structure is coupled to the first plurality of interconnect stacks.

Abstract: A bias circuit is provided that is configure to control the bias for a diode-connected transistor operating in the sub-threshold region to produce a gate-to-source voltage. A differential tuning voltage derived from the gate-to-source voltage tunes a plurality of varactors.

Abstract: The present invention discloses a plate-fin structure EGR cooler with heat-insulation function includes shell. The two ends of the shell are equipped with an air inlet flange and a discharge chamber. A water inlet pipe and a water outlet pipe are set on the shell near the air inlet flange and the discharge chamber. A cooling core assembly, an air chamber and a bellow are set in the shell. The main board at one end of the cooling core assembly is connected to the shell and the discharge chamber and the main board at another end is connected to one end of the air chamber. The other end of the air chamber is connected to one end of the bellow. The other end of the bellow is connected to the shell and the air inlet flange. A heat-insulating pipe connected to the air inlet flange is set within the bellow.

Abstract: Oscillator circuits and methods are disclosed. In an embodiment, a circuit includes a voltage controlled oscillator (VCO) and a regulator coupled to a supply input of the VCO. The circuit also includes an oscillation dampening circuit coupled to an output of the regulator. A resistance or a capacitance of the oscillation dampening circuit is configured to vary based on current provided to the VCO.

Abstract: Oscillator circuits and methods are disclosed. In an embodiment, a circuit includes a voltage controlled oscillator (VCO) and a regulator coupled to a supply input of the VCO. The circuit also includes an oscillation dampening circuit coupled to an output of the regulator. A resistance or a capacitance of the oscillation dampening circuit is configured to vary based on current provided to the VCO.

Abstract: The present invention discloses a plate-fin structure EGR cooler with heat-insulation function includes shell. The two ends of the shell are equipped with an air inlet flange and a discharge chamber. A water inlet pipe and a water outlet pipe are set on the shell near the air inlet flange and the discharge chamber. A cooling core assembly, an air chamber and a bellow are set in the shell. The main board at one end of the cooling core assembly is connected to the shell and the discharge chamber and the main board at another end is connected to one end of the air chamber. The other end of the air chamber is connected to one end of the bellow. The other end of the bellow is connected to the shell and the air inlet flange. A heat-insulating pipe connected to the air inlet flange is set within the bellow.

Abstract: A nonvolatile memory array is divided into multiple memory groups. The nonvolatile memory array receives an erase command to erase a first set of the memory groups, and not a second set of the memory groups. The control circuitry is responsive to the erase command to erase the first set of memory groups, by applying a recovery bias arrangement that adjusts threshold voltages of memory cells in at least one memory group of the second set of memory groups. By applying the recovery bias arrangement to memory cells in at least one memory group of the second set of memory groups, erase disturb is corrected during the recovery bias arrangement, at least in part.