Abstract: A facility for optimizing machine learning models is described. The facility obtains a description of a machine learning model and a hardware target for the machine learning model. The facility obtains optimization result data from a repository of optimization result data. The facility optimizes the machine learning model for the hardware target based on the optimization result data.

Abstract: A method is provided for implanting a valve having at least one valve leaflet within the cardiovascular system of a subject. One step of the method includes preparing a substantially dehydrated bioprosthetic valve and then providing an expandable support member having oppositely disposed first and second ends and a main body portion extending between the ends. Next, the substantially dehydrated bioprosthetic valve is attached to the expandable support member so that the substantially dehydrated bioprosthetic valve is operably secured within the main body portion of the expandable support member. The expandable support member is then crimped into a compressed configuration and placed at a desired location within the cardiovascular system of the subject. Either before or after placement at the desired location, fluid, or blood re-hydrates the substantially dehydrated bioprosthetic valve.

Abstract: The present disclosure generally relates to textiles that are optimized to maximize moisture wicking and evaporative performance thereof. In some embodiments, raw polyethylene (PE) powder can be extruded into fibers that can be modified by oxidation along a surface thereof to increase hydrophilicity of the surface. Once sufficiently oxidized, the fibers can be bundled to form multi-filament yarns that can then be spun, weaved, knitted, and/or otherwise associated with one another to form a polyethylene fabric. The PE fibers can be further modified to increase a capillary force of the bundle, thereby further increasing hydrophilicity of the resulting fabric. Engineering of the capillary force can be performed by optimizing one or more of a fiber size, a density, or a cross-section of the fibers and/or the bundles. The resultant fabric can exhibit a strong weight reduction, stain resistance, and drying capabilities, among other capabilities.

Abstract: A chip includes a first net, and a second net, wherein the first net and the second net are formed from a same metal layer, and the second net neighbors the first net. The chip also includes first vias disposed on the first net, and second vias disposed on the second net. A first spacing is greater than a second spacing, the first spacing is between a first one of the first vias and a second one of the first vias, the first one of the first vias and the second one of the first vias are adjacent, and the second spacing is between the first one of the first vias and one of the second vias closest to the first one of the first vias.

Abstract: An IC includes a first set of MOS transistors configured to have a common first transistor source/drain terminal A, a first transistor gate, and a first transistor source/drain terminal B. In addition, the IC includes a first plurality of interconnect stacks coupled to the first transistor source/drain terminal A. Each interconnect stack of the first plurality of interconnect stacks extends in a second direction over at least a portion of the first set of MOS transistors and includes consecutive metal layer interconnects. Further, the IC includes a first comb interconnect structure extending in a first direction orthogonal to the second direction, with comb fingers extending in the second direction over at least a portion of the first set of MOS transistors and the first plurality of interconnect stacks. The first comb interconnect structure is coupled to the first plurality of interconnect stacks.

Abstract: A bias circuit is provided that is configure to control the bias for a diode-connected transistor operating in the sub-threshold region to produce a gate-to-source voltage. A differential tuning voltage derived from the gate-to-source voltage tunes a plurality of varactors.

Abstract: Oscillator circuits and methods are disclosed. In an embodiment, a circuit includes a voltage controlled oscillator (VCO) and a regulator coupled to a supply input of the VCO. The circuit also includes an oscillation dampening circuit coupled to an output of the regulator. A resistance or a capacitance of the oscillation dampening circuit is configured to vary based on current provided to the VCO.

Abstract: Oscillator circuits and methods are disclosed. In an embodiment, a circuit includes a voltage controlled oscillator (VCO) and a regulator coupled to a supply input of the VCO. The circuit also includes an oscillation dampening circuit coupled to an output of the regulator. A resistance or a capacitance of the oscillation dampening circuit is configured to vary based on current provided to the VCO.

Abstract: A nonvolatile memory array is divided into multiple memory groups. The nonvolatile memory array receives an erase command to erase a first set of the memory groups, and not a second set of the memory groups. The control circuitry is responsive to the erase command to erase the first set of memory groups, by applying a recovery bias arrangement that adjusts threshold voltages of memory cells in at least one memory group of the second set of memory groups. By applying the recovery bias arrangement to memory cells in at least one memory group of the second set of memory groups, erase disturb is corrected during the recovery bias arrangement, at least in part.