Patents by Inventor Luis de la Torre Vega

Luis de la Torre Vega has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8060663
    Abstract: A physical layer device for interfacing with multiple computing devices includes a digital core and first and second analog front ends. The digital core is operative to perform one or more functions of the physical layer device. Each of the first and second analog front ends is operative to perform signal conversion between a digital domain and an analog domain. The physical layer device further includes a digital switching circuit coupled to the digital core and to the first and second analog front ends. The digital switching circuit is operative to electrically connect the digital core to the first analog front end or the second analog front end as a function of a control signal applied to the digital switching circuit.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: November 15, 2011
    Assignee: LSI Corporation
    Inventors: Brian P. Murray, Luis de la Torre Vega
  • Patent number: 7996166
    Abstract: In one embodiment, a method for determining capacitive signature validity of a powered device (PD) attached to power sourcing equipment (PSE) having (i) an isolated side with a primary coil and (ii) a line side with a secondary coil connected to the PD. The method includes determining, on the isolated side, a first time T1 and a corresponding first voltage V1 across the PD. Then generating, on the isolated side, a switching signal used to generate an electrical current through the primary coil. Then determining, on the isolated side, a second time T2 and a corresponding second voltage V2 across the PD, wherein a difference between V2 and V1 is related to the electrical current provided to the primary coil. Then determining the capacitive-signature validity of the PD based on T1, T2, V1, V2, and a resistive signature of the PD.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: August 9, 2011
    Assignee: Agere Systems Inc.
    Inventors: Luis de la Torre Vega, Fadi Saibi
  • Publication number: 20110029701
    Abstract: A physical layer device for interfacing with multiple computing devices includes a digital core and first and second analog front ends. The digital core is operative to perform one or more functions of the physical layer device. Each of the first and second analog front ends is operative to perform signal conversion between a digital domain and an analog domain. The physical layer device further includes a digital switching circuit coupled to the digital core and to the first and second analog front ends. The digital switching circuit is operative to electrically connect the digital core to the first analog front end or the second analog front end as a function of a control signal applied to the digital switching circuit.
    Type: Application
    Filed: July 30, 2009
    Publication date: February 3, 2011
    Inventors: Brian P. Murray, Luis de la Torre Vega
  • Patent number: 7643320
    Abstract: In one embodiment, a load connected to power sourcing equipment (PSE) compatible with a Power over Ethernet (PoE) standard is characterized to determine whether the load corresponds to a valid powered device (PD). A switching signal having a first frequency is generated on the isolated side and used to generate an electrical current through the isolated-side primary coil of a power transformer in the PSE. A first voltage measurement, corresponding to a first line-side voltage across the transformer's secondary coil, is generated on the isolated side, e.g., using an isolated-side auxiliary transformer coil. The load is characterized based on the first voltage measurement and the first frequency. To compensate for voltage offset, a second voltage measurement can be generated corresponding to a second frequency of the switching signal, where the load is then characterized based on the first and second voltage measurements and frequencies.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: January 5, 2010
    Assignee: Agere Systems Inc.
    Inventors: Luis de la Torre Vega, Fadi Saibi
  • Publication number: 20080238656
    Abstract: In one embodiment, a load connected to power sourcing equipment (PSE) compatible with a Power over Ethernet (PoE) standard is characterized to determine whether the load corresponds to a valid powered device (PD). A switching signal having a first frequency is generated on the isolated side and used to generate an electrical current through the isolated-side primary coil of a power transformer in the PSE. A first voltage measurement, corresponding to a first line-side voltage across the transformer's secondary coil, is generated on the isolated side, e.g., using an isolated-side auxiliary transformer coil. The load is characterized based on the first voltage measurement and the first frequency. To compensate for voltage offset, a second voltage measurement can be generated corresponding to a second frequency of the switching signal, where the load is then characterized based on the first and second voltage measurements and frequencies.
    Type: Application
    Filed: March 28, 2007
    Publication date: October 2, 2008
    Applicant: AGERE SYSTEMS INC.
    Inventors: Luis de la Torre Vega, Fadi Saibi
  • Publication number: 20080238447
    Abstract: In one embodiment, a method for determining capacitive signature validity of a powered device (PD) attached to power sourcing equipment (PSE) having (i) an isolated side with a primary coil and (ii) a line side with a secondary coil connected to the PD. The method includes determining, on the isolated side, a first time T1 and a corresponding first voltage V1 across the PD. Then generating, on the isolated side, a switching signal used to generate an electrical current through the primary coil. Then determining, on the isolated side, a second time T2 and a corresponding second voltage V2 across the PD, wherein a difference between V2 and V1 is related to the electrical current provided to the primary coil. Then determining the capacitive-signature validity of the PD based on T1, T2, V1, V2, and a resistive signature of the PD.
    Type: Application
    Filed: March 26, 2007
    Publication date: October 2, 2008
    Applicant: Agere Systems Inc.
    Inventors: Luis de la Torre Vega, Fadi Saibi