Patents by Inventor Luis Elvira
Luis Elvira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10639012Abstract: The present invention relates to a method for measuring circulating cells in superficial body fluids by means of high-frequency-based device. The method can be used for detecting circulating cells in the fluids of an individual without the necessity of extracting a sample of the individual, being useful as a diagnostic tool and for monitoring the effectiveness of a treatment administered to an individual suffering from a viral, protozoal, fungal and/or bacterial disease.Type: GrantFiled: September 19, 2016Date of Patent: May 5, 2020Assignees: CONSEJO SUPERIOR DE INVESTIGACIONES CIENTIFICAS (CSIC), FUNDACION PARA EL CONOCIMIENTO MADRI+D, MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: Luis Elvira Segura, Oscar Martinez Graullera, Shiva Kant Shukla, Francisco Montero, Javier Jimenez, Ian Richard Butterworth, Brian Anthony, John Lee Haeseon, Carlos Castro Gonzalez
-
Publication number: 20180263602Abstract: The present invention relates to a method for measuring circulating cells in superficial body fluids by means of high-frequency-based device. The method can be used for detecting circulating cells in the fluids of an individual without the necessity of extracting a sample of the individual, being useful as a diagnostic tool and for monitoring the effectiveness of a treatment administered to an individual suffering from a viral, protozoal, fungal and/or bacterial disease.Type: ApplicationFiled: September 19, 2016Publication date: September 20, 2018Inventors: Luis ELVIRA SEGURO, Oscar MARTINEZ GRAULLERA, Shiva KANT SHUKLA, Francisco MONTERO, Javier JIMENEZ, Ian Richard BUTTERWORTH, Brian ANTHONY, John HEASON LEE, Carlos CASTRO GONZALEZ
-
Patent number: 9557302Abstract: An ultrasound inspection roller provided with a wheel, a sensing system and a support for holding the sensing system inside the wheel, a wedge connected to the ultrasound sensing system at one end and provided with a curved profile at its other end facing the wheel, adapted to the curvilinear shape of the wheel, and a liquid of a density higher than 9.9*102 kg/mm3 placed inside the wheel such that the sensory system, the wheel and the wedge are acoustically coupled. The roller allows the early detection of problems during manufacturing of composites and the performance of corrective measures in real time, and assures a good coupling between the transducers and the material to be inspected in dry conditions.Type: GrantFiled: December 3, 2013Date of Patent: January 31, 2017Assignee: Airbus Operations S.L.Inventors: Carlos De Miguel Giraldo, Gildas Lambert, Oscar Martinez, Luis Elvira, David Romero, Luis Gomez Ullate, Francisco Montero
-
Publication number: 20140150557Abstract: An ultrasound inspection roller provided with a wheel, a sensing system and a support for holding the sensing system inside the wheel, a wedge connected to the ultrasound sensing system at one end and provided with a curved profile at its other end facing the wheel, adapted to the curvilinear shape of the wheel, and a liquid of a density higher than 9.9*102 kg/mm3 placed inside the wheel such that the sensory system, the wheel and the wedge are acoustically coupled. The roller allows the early detection of problems during manufacturing of composites and the performance of corrective measures in real time, and assures a good coupling between the transducers and the material to be inspected in dry conditions.Type: ApplicationFiled: December 3, 2013Publication date: June 5, 2014Inventors: Carlos De Miguel Giraldo, Gildas Lambert, Oscar Martinez, Luis Elvira, David Romero, Luis Gomez Ullate, Francisco Montero
-
Patent number: 8531204Abstract: Disclosed is an integrated circuit (200) comprising a plurality of cores (110, 110), at least some of the cores being located in different power domains (VDD1, VDD2), each core being surrounded by a test wrapper (220) comprising a plurality of wrapper cells (128, 230), wherein each of said test wrappers are located in a single power domain (VDD3) and each plurality of wrapper cells comprises wrapper output cells (230) each arranged to output a signal from its associated core, each of said wrapper output cells comprising an output level shifter (232, 240) for shifting the voltage of said signal to the voltage of the single power domain (VDD3). A method for testing such an IC and standard library cells for designing such an IC are also disclosed.Type: GrantFiled: November 10, 2009Date of Patent: September 10, 2013Assignee: NXP, B.V.Inventors: Rinze Ida Mechtildis Peter Meijer, Luis Elvira Villagra
-
Patent number: 8138783Abstract: A circuit portion (100) of an IC comprises a plurality of conductive tracks (130) for coupling respective circuit portion elements (150), e.g. standard logic cells, to a power supply rail (110), with the conductive tracks (130) being coupled to the power supply rail (110) via at least one enable switch (132). The circuit portion (100) further comprising an element (160) for determining a voltage gradient over the circuit portion (100) in a test mode of the integrated circuit (600), which is conductively coupled to the conductive tracks (130). The element (160) has a first end portion (164) for coupling the element (160) to the power supply terminal and a second end portion (166) for coupling the element (160) to the output (620) in the test mode. This facilitates IDDQ testing of the circuit portion (100) by means of measuring a voltage gradient over the element (160).Type: GrantFiled: September 4, 2007Date of Patent: March 20, 2012Assignee: NXP B.V.Inventors: Josep Rius Vazquez, Luis Elvira Villagra, Rinze I. M. P. Meijer
-
Patent number: 8107288Abstract: A semiconductor memory device includes n-wells (22) and p-wells (24) used to make up a plurality of memory cell elements (40). The n-wells (22) and p-5 wells (24) can be back-biased to improve reading and writing performance. One of the n-wells and p-wells can be globally biased while the other one of the n-wells and p-wells can be biased by groups, such as blocks, rows or columns. Error reduction and/or correction can be performed by adjusting the well bias.Type: GrantFiled: June 25, 2008Date of Patent: January 31, 2012Assignee: NXP B.V.Inventors: Luis Elvira Villagra, Rinze L. M. Meijer, Jose De Jesus Pineda De Gyvez
-
Publication number: 20110221502Abstract: Disclosed is an integrated circuit (200) comprising a plurality of cores (110, 110), at least some of the cores being located in different power domains (VDD1, VDD2), each core being surrounded by a test wrapper (220) comprising a plurality of wrapper cells (128, 230), wherein each of said test wrappers are located in a single power domain (VDD3) and each plurality of wrapper cells comprises wrapper output cells (230) each arranged to output a signal from its associated core, each of said wrapper output cells comprising an output level shifter (232, 240) for shifting the voltage of said signal to the voltage of the single power domain (VDD3). A method for testing such an IC and standard library cells for designing such an IC are also disclosed.Type: ApplicationFiled: November 10, 2009Publication date: September 15, 2011Applicant: NXP B.V.Inventors: Rinze Ida Mechtildis Peter Meijer, Luis Elvira Villagra
-
Publication number: 20110205787Abstract: A Static Random Access Memory comprising a matrix arrangement of cells, each cell comprising:—a bistable loop of a first inverter and a second inverter, in which an input of the first inverter is coupled to an output of the second inverter at a first bistable node and an input of the second inverter is coupled to an output of the first inverter at a second bistable node;—a first access transistor connected between the first bistable node and a write bitline, the first access transistor having a control terminal connected to a write wordline, and—a second access transistor connected between the second bistable node and a line being the complement of the write bitline, the second access transistor having a control terminal connected to the write wordline wherein—a first separate read port is connected between a read bitline and a source potential, which first read port has at least two control terminals, one control terminal being connected to the second bistable node and one to a read wordline, and—a second seType: ApplicationFiled: October 12, 2009Publication date: August 25, 2011Applicant: NXP B.V.Inventors: Roelof Herman Willem Salters, Tobias Sebastiaan Doorn, Luis Elvira Villagra
-
Publication number: 20100202192Abstract: A semiconductor memory device includes n-wells (22) and p-wells (24) used to make up a plurality of memory cell elements (40). The n-wells (22) and p-5 wells (24) can be back-biased to improve reading and writing performance. One of the n-wells and p-wells can be globally biased while the other one of the n-wells and p-wells can be biased by groups, such as blocks, rows or columns. Error reduction and/or correction can be performed by adjusting the well bias.Type: ApplicationFiled: June 25, 2008Publication date: August 12, 2010Applicant: NXP B.V.Inventors: Luis Elvira Villagra, Rinze L.M. Meijer, Jose De Jesus Pineda De Gyvez
-
Publication number: 20090315583Abstract: A circuit portion (100) of an IC comprises a plurality of conductive tracks (130) for coupling respective circuit portion elements (150), e.g. standard logic cells, to a power supply rail (110), with the conductive tracks (130) being coupled to the power supply rail (110) via at least one enable switch (132). The circuit portion (100) further comprising an element (160) for determining a voltage gradient over the circuit portion (100) in a test mode of the integrated circuit (600), which is conductively coupled to the conductive tracks (130). The element (160) has a first end portion (164) for coupling the element (160) to the power supply terminal and a second end portion (166) for coupling the element (160) to the output (620) in the test mode. This facilitates IDDQ testing of the circuit portion (100) by means of measuring a voltage gradient over the element (160).Type: ApplicationFiled: September 4, 2007Publication date: December 24, 2009Applicant: NXP, B.V.Inventors: Josep Rius Vazquez, Luis Elvira Villagra, Rinze I.M.P. Meijer
-
Patent number: 7240553Abstract: The invention relates to a method and a device for the early detection of the presence of micro-organisms in food, particularly in milk and derivatives thereof. One of the main advantages of the invention lies in the fact that the aforementioned detection method can be performed inside the commercial packaging thereof without the need for said packaging to be opened. The presence of micro-organism is detected, before they can produce drastic changes in the physical properties of the product, according to changes in the propagation of elastic waves (velocity, attenuation and harmonic distortion) through the product and, moreover, different types of micro-organisms can be distinguished. The inventive detection method is performed under dry conditions and requires an environment with controlled humidity and temperature.Type: GrantFiled: December 13, 2004Date of Patent: July 10, 2007Assignees: Consejo Superior De Investigaciones Cientificas (CSIC), Corporacion Alimentaria Penasanta, S. A.Inventors: Luis Elvira Segura, Francisco Montero de Espinosa Freijo, Pablo Resa López, Yago Gomez-Ullate Ricon
-
Patent number: 6351895Abstract: The invention relates to a method for making the drying of materials, particularly finely divided materials, more effective, in which method, of a slurry containing liquid and solids there is made a filter cake (2,12,22) onto the surface of the filter medium (1,11,21). According to the invention, the filter cake (2,12,22) and the oscillator (6,15,25) are arranged, in relation to each other, so that in between the filter cake (2,12,22) and the oscillator (6,15,25), there is generated an acoustic field by virtue of a mechanical contact between the filter cake (2,12,22) and the oscillator (6,15,25) or a structural element (7,16,26) connected to the oscillator.Type: GrantFiled: June 4, 1999Date of Patent: March 5, 2002Assignee: Outokumpu OyjInventors: Bjarne Ekberg, Göran Norrgård, Juan A. Gallego Juárez, Germán Rodriguez Corral, Luis Elvira Segura
-
Patent number: 6079120Abstract: The invention relates to a method for making the drying finely divided materials, more effective in a suction drier provided with a fine porous suction surface, where the radii of the fine pores of the suction surface are essentially within the range of 0.5-2 micrometers, and in which method, of a slurry containing liquid and solids there is made a filter cake (2,12,22) onto a fine porous liquid suction surface constituting the filter surface of the filter medium (1,11,21), According to the invention, the filter cake (2,12,22) and an oscillator (6,15,25) are arranged, in relation to each other, so that in between the filter cake (2,12,22) and the oscillator (6,15,25), there is generated an acoustic field by virtue of a mechanical contact between the filter cake (2,12,22) and the oscillator (6,15,25) or a structural element (7,16,26) connected to the oscillator.Type: GrantFiled: June 4, 1999Date of Patent: June 27, 2000Assignee: Outokumpu OyjInventors: Bjarne Ekberg, Goran Norrg.ang.rd, Juan A. Gallego Juarez, German Rodriguez Corral, Luis Elvira Segura