Abstract: Disclosed is an integrated circuit (200) comprising a plurality of cores (110, 110), at least some of the cores being located in different power domains (VDD1, VDD2), each core being surrounded by a test wrapper (220) comprising a plurality of wrapper cells (128, 230), wherein each of said test wrappers are located in a single power domain (VDD3) and each plurality of wrapper cells comprises wrapper output cells (230) each arranged to output a signal from its associated core, each of said wrapper output cells comprising an output level shifter (232, 240) for shifting the voltage of said signal to the voltage of the single power domain (VDD3). A method for testing such an IC and standard library cells for designing such an IC are also disclosed.

Abstract: A circuit portion (100) of an IC comprises a plurality of conductive tracks (130) for coupling respective circuit portion elements (150), e.g. standard logic cells, to a power supply rail (110), with the conductive tracks (130) being coupled to the power supply rail (110) via at least one enable switch (132). The circuit portion (100) further comprising an element (160) for determining a voltage gradient over the circuit portion (100) in a test mode of the integrated circuit (600), which is conductively coupled to the conductive tracks (130). The element (160) has a first end portion (164) for coupling the element (160) to the power supply terminal and a second end portion (166) for coupling the element (160) to the output (620) in the test mode. This facilitates IDDQ testing of the circuit portion (100) by means of measuring a voltage gradient over the element (160).

Abstract: A semiconductor memory device includes n-wells (22) and p-wells (24) used to make up a plurality of memory cell elements (40). The n-wells (22) and p-5 wells (24) can be back-biased to improve reading and writing performance. One of the n-wells and p-wells can be globally biased while the other one of the n-wells and p-wells can be biased by groups, such as blocks, rows or columns. Error reduction and/or correction can be performed by adjusting the well bias.

Abstract: Disclosed is an integrated circuit (200) comprising a plurality of cores (110, 110), at least some of the cores being located in different power domains (VDD1, VDD2), each core being surrounded by a test wrapper (220) comprising a plurality of wrapper cells (128, 230), wherein each of said test wrappers are located in a single power domain (VDD3) and each plurality of wrapper cells comprises wrapper output cells (230) each arranged to output a signal from its associated core, each of said wrapper output cells comprising an output level shifter (232, 240) for shifting the voltage of said signal to the voltage of the single power domain (VDD3). A method for testing such an IC and standard library cells for designing such an IC are also disclosed.

Abstract: A Static Random Access Memory comprising a matrix arrangement of cells, each cell comprising:—a bistable loop of a first inverter and a second inverter, in which an input of the first inverter is coupled to an output of the second inverter at a first bistable node and an input of the second inverter is coupled to an output of the first inverter at a second bistable node;—a first access transistor connected between the first bistable node and a write bitline, the first access transistor having a control terminal connected to a write wordline, and—a second access transistor connected between the second bistable node and a line being the complement of the write bitline, the second access transistor having a control terminal connected to the write wordline wherein—a first separate read port is connected between a read bitline and a source potential, which first read port has at least two control terminals, one control terminal being connected to the second bistable node and one to a read wordline, and—a second se

Abstract: A semiconductor memory device includes n-wells (22) and p-wells (24) used to make up a plurality of memory cell elements (40). The n-wells (22) and p-5 wells (24) can be back-biased to improve reading and writing performance. One of the n-wells and p-wells can be globally biased while the other one of the n-wells and p-wells can be biased by groups, such as blocks, rows or columns. Error reduction and/or correction can be performed by adjusting the well bias.

Abstract: A circuit portion (100) of an IC comprises a plurality of conductive tracks (130) for coupling respective circuit portion elements (150), e.g. standard logic cells, to a power supply rail (110), with the conductive tracks (130) being coupled to the power supply rail (110) via at least one enable switch (132). The circuit portion (100) further comprising an element (160) for determining a voltage gradient over the circuit portion (100) in a test mode of the integrated circuit (600), which is conductively coupled to the conductive tracks (130). The element (160) has a first end portion (164) for coupling the element (160) to the power supply terminal and a second end portion (166) for coupling the element (160) to the output (620) in the test mode. This facilitates IDDQ testing of the circuit portion (100) by means of measuring a voltage gradient over the element (160).