Abstract: A low power relaxation oscillator circuit includes, in one embodiment, a first comparator for comparing voltages at first and second inputs, respectively, a first capacitor coupled to the first input of the first comparator, and a first circuit configured for charging the first capacitor to a first voltage. The first voltage is related to a propagation delay of the first comparator.

Abstract: A low power relaxation oscillator circuit includes, in one embodiment, a first comparator for comparing voltages at first and second inputs, respectively, a first capacitor coupled to the first input of the first comparator, and a first circuit configured for charging the first capacitor to a first voltage. The first voltage is related to a propagation delay of the first comparator.

Abstract: A sample and hold circuit configured to sample a current includes an input node to receive the current, a capacitor coupled with a sampling node and a reference voltage node, switch between the input node and the sampling node, a controlled current source coupled to the input node, a current mirror circuit having connections each providing a mirrored current, wherein at least one of said connections provides an output node, and a transistor arrangement. The transistor arrangement includes a control MOSFET in series with a series connected chain of cascaded cells. The control MOSFET and each of said cascaded cells are coupled to the current mirror circuit and each of the cascaded cells includes a pair of MOSFETs arranged to provide a voltage difference including a difference between a gate-source voltage of a first of the pair and a gate-source voltage of a second of the pair.

Abstract: A sample and hold circuit configured to sample a current includes an input node to receive the current, a capacitor coupled with a sampling node and a reference voltage node, switch between the input node and the sampling node, a controlled current source coupled to the input node, a current mirror circuit having connections each providing a mirrored current, wherein at least one of said connections provides an output node, and a transistor arrangement. The transistor arrangement includes a control MOSFET in series with a series connected chain of cascaded cells. The control MOSFET and each of said cascaded cells are coupled to the current mirror circuit and each of the cascaded cells includes a pair of MOSFETs arranged to provide a voltage difference including a difference between a gate-source voltage of a first of the pair and a gate-source voltage of a second of the pair.

Abstract: A bias circuit is provided. The bias circuit includes a comparator circuit configured to compare a first voltage at a first input with a second voltage at a second input and generate a digital value at an output. A level shifter circuit is coupled to the comparator circuit. The level shifter is configured to receive a reference voltage at an input and generate the second voltage at an output. A charge pump circuit is coupled to the comparator circuit. The charge pump circuit is configured to generate the first voltage at an output based on the digital value.

Abstract: A regulator clamp circuit includes a comparison circuit having a sample and hold circuit. The comparison circuit compares a regulated voltage with a sampled voltage of the regulated voltage from a previous time. In some embodiments, the sampled voltage can be determined during a sampling phase that occurs prior to a clamp regulation phase. During the clamp regulation phase, the comparison circuit compares the regulated voltage with the sampled voltage and outputs a signal to activate an actuator circuit to clamp the regulated voltage when the regulated voltage terminal has a higher amount of charge than desired.

Abstract: Regulation systems and methods use a first regulator and a tracking second regulator. The first regulator receives a reference voltage and generates a first voltage output based upon the reference voltage, which is coupled as a back-bias voltage to a first load region within the integrated circuit. The first regulator also receives a sampled version of the first voltage output as feedback. A second regulator receives the first sampled voltage output and generates a second voltage output. The second regulator also receives a sampled version of the second voltage output as feedback. During operation, the second voltage output tracks (e.g., by a symmetry ratio) the first voltage output and is coupled as a back-bias voltage to a second load region within the integrated circuit. Further, switched-capacitor operation can be implemented, and clock frequency can be adjusted based upon the first sampled voltage output to reduce power consumption.