Abstract: A facility for optimizing machine learning models is described. The facility obtains a description of a machine learning model and a hardware target for the machine learning model. The facility obtains optimization result data from a repository of optimization result data. The facility optimizes the machine learning model for the hardware target based on the optimization result data.

Abstract: A facility for optimizing machine learning models is described. The facility obtains a description of a machine learning model and a hardware target for the machine learning model. The facility obtains optimization result data from a repository of optimization result data. The facility optimizes the machine learning model for the hardware target based on the optimization result data.

Abstract: A facility for optimizing machine learning models is described. The facility obtains a description of a machine learning model and a hardware target for the machine learning model. The facility obtains optimization result data from a repository of optimization result data. The facility optimizes the machine learning model for the hardware target based on the optimization result data.

Abstract: A facility for optimizing machine learning models is described. The facility obtains a description of a machine learning model and a hardware target for the machine learning model. The facility obtains optimization result data from a repository of optimization result data. The facility optimizes the machine learning model for the hardware target based on the optimization result data.

Abstract: A facility for optimizing machine learning models is described. The facility obtains a description of a machine learning model and a hardware target for the machine learning model. The facility obtains optimization result data from a repository of optimization result data. The facility optimizes the machine learning model for the hardware target based on the optimization result data.

Abstract: A facility for optimizing machine learning models is described. The facility obtains a description of a machine learning model and a hardware target for the machine learning model. The facility obtains optimization result data from a repository of optimization result data. The facility optimizes the machine learning model for the hardware target based on the optimization result data.

Abstract: A facility for optimizing machine learning models is described. The facility obtains a description of a machine learning model and a hardware target for the machine learning model. The facility obtains optimization result data from a repository of optimization result data. The facility optimizes the machine learning model for the hardware target based on the optimization result data.

Abstract: A facility for optimizing machine learning models is described. The facility obtains a description of a machine learning model and a hardware target for the machine learning model. The facility obtains optimization result data from a repository of optimization result data. The facility optimizes the machine learning model for the hardware target based on the optimization result data.

Abstract: In some embodiments, systems and methods for storing and/or retrieving digital information in a nucleic acid library are provided. In some embodiments, an integrated system comprising a nucleic acid synthesis device, a nucleic acid sequencing device, a computing device, and a nucleic acid library is provided. In some embodiments, a write request that associates a value with a key is received by the system, the system synthesizes nucleic acid molecules associated with the request, and stores the nucleic acid molecules in the nucleic acid library. In some embodiments, a read request for a key is received by the system, and the system sequences nucleic acid molecules from the nucleic acid library that are associated with the key.

Abstract: In some embodiments, systems and methods for storing and/or retrieving digital information in a nucleic acid library are provided. In some embodiments, an integrated system comprising a nucleic acid synthesis device, a nucleic acid sequencing device, a computing device, and a nucleic acid library is provided. In some embodiments, a write request that associates a value with a key is received by the system, the system synthesizes nucleic acid molecules associated with the request, and stores the nucleic acid molecules in the nucleic acid library. In some embodiments, a read request for a key is received by the system, and the system sequences nucleic acid molecules from the nucleic acid library that are associated with the key.

Abstract: A memory chip for dynamic approximate storage includes an array of memory cells associated with at least two regions. The chip further includes at least one threshold register for storing values for thresholds for memory cells corresponding to each of the at least two regions; and control logic to programmatically adjust the values for the thresholds for the memory cells. A method of controlling a storage device for dynamic approximate storage includes modifying at least one value stored in a threshold register and associated with at least one cell in a region of a memory comprising at least two regions to apply a biasing for the at least one cell, wherein the biasing adjusts ranges for values in a cell.

Abstract: A method of encoding data on single level or variable multi-level cell storage includes receiving a block of encoded data from an approximation-aware application and at least an importance attribute associated with the block of encoded data; and assigning the block of encoded data to a memory address or a particular region of a memory having at least three precision levels, based at least according to the importance attribute. The importance attribute indicates a relative sensitivity of bits of the block to errors in an output quality from decoding the encoded data. An approximation-aware application can be an image encoding application having a modified entropy encoding step that enables identification and splitting of bits into groupings according to sensitivity to errors.

Abstract: A memory chip for dynamic approximate storage includes an array of memory cells associated with at least two regions. The chip further includes at least one threshold register for storing values for thresholds for memory cells corresponding to each of the at least two regions; and control logic to programmatically adjust the values for the thresholds for the memory cells. A method of controlling a storage device for dynamic approximate storage includes modifying at least one value stored in a threshold register and associated with at least one cell in a region of a memory comprising at least two regions to apply a biasing for the at least one cell, wherein the biasing adjusts ranges for values in a cell.

Abstract: A method of encoding data on single level or variable multi-level cell storage includes receiving a block of encoded data from an approximation-aware application and at least an importance attribute associated with the block of encoded data; and assigning the block of encoded data to a memory address or a particular region of a memory having at least three precision levels, based at least according to the importance attribute. The importance attribute indicates a relative sensitivity of bits of the block to errors in an output quality from decoding the encoded data. An approximation-aware application can be an image encoding application having a modified entropy encoding step that enables identification and splitting of bits into groupings according to sensitivity to errors.

Abstract: The present technology relaxes the precision (or full data-correctness-guarantees) requirements in memory operations, such as writing or reading, of MLC memories so that an application may write and read a digital data value as an approximate value. Types of MLCs include Flash MLC and MLC Phase Change Memory (PCM) as well as other resistive technologies. Many software applications may not need the accuracy or precision typically used to store and read data values. For example, an application may render an image on a relatively low resolution display and may not need an accurate data value for each pixel. By relaxing the precision or correctness requirements is a memory operation, MLC memories may have increased performance, lifetime, density, and/or energy efficiency.

Abstract: Devices and methods for providing deterministic execution of multithreaded applications are provided. In some embodiments, each thread is provided access to an isolated memory region, such as a private cache. In some embodiments, more than one private cache are synchronized via a modified MOESI coherence protocol. The modified coherence protocol may be configured to refrain from synchronizing the isolated memory regions until the end of an execution quantum. The execution quantum may end when all threads experience a quantum end event such as reaching a threshold instruction count, overflowing the isolated memory region, and/or attempting to access a lock released by a different thread in the same quantum.

Abstract: A system and method are provided for enhancing approximate computing by a computer system. In one example, an interface is provided comprising a variable-identifier module and a bit-priority module. The variable-identifier module is configured to identify one or more variables of data that are to be processed by the computer system with approximate precision. Approximate precision is a precision level at which a hardware device does not guarantee full data-correctness for the one or more variables. The bit-priority module is configured to assign bit-priorities to the one or more variables. The bit-priorities include relative levels of importance among bits of each of the one or more variables. The relative levels of importance include at least high-priority bits and low-priority bits.

Abstract: The present technology relaxes the precision (or full data-correctness-guarantees) requirements in memory operations, such as writing or reading, of MLC memories so that an application may write and read a digital data value as an approximate value. Types of MLCs include Flash MLC and MLC Phase Change Memory (PCM) as well as other resistive technologies. Many software applications may not need the accuracy or precision typically used to store and read data values. For example, an application may render an image on a relatively low resolution display and may not need an accurate data value for each pixel. By relaxing the precision or correctness requirements is a memory operation, MLC memories may have increased performance, lifetime, density, and/or energy efficiency.

Abstract: The present technology relaxes the precision (or full data-correctness-guarantees) requirements in memory operations, such as writing or reading, of MLC memories so that an application may write and read a digital data value as an approximate value. Types of MLCs include Flash MLC and MLC Phase Change Memory (PCM) as well as other resistive technologies. Many software applications may not need the accuracy or precision typically used to store and read data values. For example, an application may render an image on a relatively low resolution display and may not need an accurate data value for each pixel. By relaxing the precision or correctness requirements is a memory operation, MLC memories may have increased performance, lifetime, density, and/or energy efficiency.

Abstract: The present technology relaxes the precision (or full data-correctness-guarantees) requirements in memory operations, such as writing or reading, of MLC memories so that an application may write and read a digital data value as an approximate value. Types of MLCs include Flash MLC and MLC Phase Change Memory (PCM) as well as other resistive technologies. Many software applications may not need the accuracy or precision typically used to store and read data values. For example, an application may render an image on a relatively low resolution display and may not need an accurate data value for each pixel. By relaxing the precision or correctness requirements is a memory operation, MLC memories may have increased performance, lifetime, density, and/or energy efficiency.