Abstract: Methods, systems, and apparatuses include probabilistically determining a read operation number using a window size. A read command is received from a host device by a memory subsystem. A memory address is determined using the read command. It is determined that the read command corresponds to the read operation number. The memory address is flagged to have a select gate of the memory address scanned. The select gate of the memory address is scanned in response to flagging the memory address.

Abstract: Methods, systems, and apparatuses include probabilistically determining a read operation number using a window size. A read command is received from a host device by a memory subsystem. A memory address is determined using the read command. It is determined that the read command corresponds to the read operation number. The memory address is flagged to have a select gate of the memory address scanned. The select gate of the memory address is scanned in response to flagging the memory address.

Abstract: Methods, systems, and devices for pre-erasing memory blocks are described. Multiple memory cells of multiple available memory cells may be erased to obtain multiple erased memory cells. Subsequent programming of the multiple erased memory cells may be delayed for a duration. Based on delaying the subsequent programming of the multiple erased memory cells for the duration, the multiple erased memory cells may be programmed.

Abstract: Methods, systems, and devices for techniques to manage parity information for data transfer operations are described. A memory system may produce additional parity information for data to be stored in a set of multi-level memory cells. The memory system may receive a command to store data and may determine whether a destination physical address for the data includes a weak word line using a mapping. The memory system may generate parity information for the data using a mapping between a first set of single-level memory cells and a second set of multi-level memory cells configured to store multiple bits of data. The memory system may store the data and the parity information to the first set of single-level memory cells and may transfer the data and the parity information from the first set of single-level memory cells to the second set of multi-level memory cells.

Abstract: This disclosure configures a memory sub-system controller to dynamically compute a select gate (SG) scan threshold. The controller accesses a default cadence criterion associated with an individual portion of a set of memory components and computes a new cadence criterion for the individual portion of the set of memory components based on the default cadence criterion. The controller determines that current cadence information for the individual portion of the set of memory components satisfies the new cadence criterion. The controller, in response to determining that current cadence information for the individual portion of the set of memory components satisfies the new cadence criterion, applies a memory operation to test reliability of the individual portion and selectively retires the individual portion based on a result of testing the reliability of the individual portion.

Abstract: Various embodiments provide for performance of a coarse threshold estimate (CTE) read on a memory device of a memory system under multi-plane mode, such as a memory sub-system.