Abstract: A computer-implemented method includes determining a current state and a current context of an environment in which an automated agent runs to execute a contingent plan. The state indicates that one or more fluents of a plurality of fluents are true, and the plurality of fluents are associated with a contingent problem solved by the contingent plan. The context describes values corresponding to the one or more fluents. An action is performed with respect to at least a subset of the context. A nondeterministic effect of the action on the environment is evaluated, using a computer processor. The state is updated based on the nondeterministic effect. The context is updated based on the nondeterministic effect.

Abstract: A persistent memory storage system and method of operating. The storage system is embodied as memory module (e.g., a DIMM or PCIe card) in a host server and accessible via a first access path to/from the memory module. After a power failure at the host server, any authorized device, e.g., a second server, is configured to access and extract the retained memory at the failed host server via a secondary network-based access path (e.g., Ethernet connection). Power may be supplied to the memory module of the failed host server via a Power-over-Ethernet switch to support the secondary access path. A Power-over-Ethernet (PoE) switch may provide the necessary power to the memory module when power is unavailable from the host server and when any temporary power source is exhausted. A redundant power source and/or backup battery may supply the PoE switch. Such power sources and/or batteries can thereby provide backup power.

Abstract: A computer-implemented method includes determining a current state and a current context of an environment in which an automated agent runs to execute a contingent plan. The state indicates that one or more fluents of a plurality of fluents are true, and the plurality of fluents are associated with a contingent problem solved by the contingent plan. The context describes values corresponding to the one or more fluents. An action is performed with respect to at least a subset of the context. A nondeterministic effect of the action on the environment is evaluated, using a computer processor. The state is updated based on the nondeterministic effect. The context is updated based on the nondeterministic effect.

Abstract: A persistent memory storage system and method of operating. The storage system is embodied as memory module (e.g., a DIMM or PCIe card) in a host server and accessible via a first access path to/from the memory module. After a power failure at the host server, any authorized device, e.g., a second server, is configured to access and extract the retained memory at the failed host server via a secondary network-based access path (e.g., Ethernet connection). Power may be supplied to the memory module of the failed host server via a Power-over-Ethernet switch to support the secondary access path. A Power-over-Ethernet (PoE) switch may provide the necessary power to the memory module when power is unavailable from the host server and when any temporary power source is exhausted. A redundant power source and/or backup battery may supply the PoE switch. Such power sources and/or batteries can thereby provide backup power.

Abstract: In one exemplary embodiment of the invention, a method includes: receiving a first description for a circuit whose operation over a plurality of inputs is to be verified; receiving a second description for expected behavior of the circuit, where the expected behavior in the second description is expressed as a set of algebraic systems of multivariable polynomials over at least one Galois field; applying at least one computational algebraic geometry technique to a combination of the first description and the second description to determine whether the circuit is verified, where verification of the circuit confirms that at least one output obtained based on the first description corresponds to at least one expected value based on the expected behavior expressed in the second description; and outputting an indication as to whether the circuit is verified.

Abstract: In one exemplary embodiment of the invention, a method includes: receiving a first description for a circuit whose operation over a plurality of inputs is to be verified; receiving a second description for expected behavior of the circuit, where the expected behavior in the second description is expressed as a set of algebraic systems of multivariable polynomials over at least one Galois field; applying at least one computational algebraic geometry technique to a combination of the first description and the second description to determine whether the circuit is verified, where verification of the circuit confirms that at least one output obtained based on the first description corresponds to at least one expected value based on the expected behavior expressed in the second description; and outputting an indication as to whether the circuit is verified.

Abstract: A system for memory management including a tag cache in communication with one or more cache devices in a storage hierarchy is provided. The tag cache includes tags of recently accessed memory blocks, each tag corresponding to one of the memory blocks and each tag including tag contents. The tag contents include a memory block real address and one bit for every memory line in the memory block. The bits are referred to as prefetch bits. Each of the prefetch bits is reset to a non-prefetch status with a selected probability of between zero and one. The tag contents control which memory lines of the corresponding memory block are prefetched into at least one of the cache devices. The tag contents are updated using a selected subset of processor references. The subset is referred to as filtered references. The tag contents are modified probabilistically at selected times or events.

Abstract: Arrangements and methods for developing a software toolkit that can be used to design or obtain parameters for a sensor network. High-level guidelines on the basic relations between sensor network parameters like number of sensors, degree of quantization at each sensor, and the distortion requirements, based on a deep analysis on two basic coding possibilities (multiplexed point-to-point, distributed) are contemplated. By evaluating tradeoffs among the various parameters, an optimization framework to obtain the most cost-effective design with required quantization capabilities pertaining to given distortion criterion is provided.

Abstract: A method and system for memory management are provided. The system includes a tag cache in communication with one or more cache devices in a storage hierarchy. The tag cache includes tags of recently accessed memory blocks, each tag corresponding to one of the memory blocks and including tag contents. The tag contents control which memory lines of the corresponding memory block are prefetched into at least one of the cache devices. The tag contents further include a bit to control prefetching of memory lines from a next virtual memory block, the bit referred to as a next virtual memory block bit. The next virtual memory block bit in a preceding memory block in a virtual address space is set to a prefetch status when the preceding memory block tag is in the tag cache.

Abstract: We present a “directory extension” (hereinafter “DX”) to aid in prefetching between proximate levels in a cache hierarchy. The DX may maintain (1) a list of pages which contains recently ejected lines from a given level in the cache hierarchy, and (2) for each page in this list, the identity of a set of ejected lines, provided these lines are prefetchable from, for example, the next level of the cache hierarchy. Given a cache fault to a line within a page in this list, other lines from this page may then be prefetched without the substantial overhead to directory lookup which would otherwise be required.

Abstract: A system for memory management including a tag cache in communication with one or more cache devices in a storage hierarchy. The tag cache includes tags of recently accessed memory blocks where each tag corresponds to one of the pages and each tag includes tag contents. The tag contents control which memory lines of the corresponding memory block are prefetched into at least one of the cache devices. The tag contents are updated using a selected subset of processor references. The subset is referred to as filtered references. The tag contents are modified probabilistically at selected time or events.

Abstract: A system for memory management including a tag controlled buffer in communication with a memory device. The memory device includes a plurality of pages divided into a plurality of individually addressable lines. The tag controlled buffer includes a prefetch buffer including at least one of the individually addressable lines from the memory device. The tag controlled buffer also includes a tag cache in communication with the prefetch buffer. The tag cache includes a plurality of tags, where each tag is associated with one of the pages in the memory device and each tag includes a pointer to at least one of the lines in the prefetch buffer. Access to the lines in the prefetch buffer is controlled by the tag cache.

Abstract: A system and method of detecting and forecasting resource bottlenecks of a computer system. In one aspect, a method comprises the steps of: monitoring with successive measurements a utilization parameter of a system resource; computing a change parameter by comparing the differences between successive measurements of the utilization parameter; comparing the change parameter to a threshold change parameter; and reporting a resource bottleneck if the change parameter exceeds the threshold change parameter.