Abstract: A circuit arrangement is described with a sense latch for increasing the number of dynamic FET storage cells on bit lines (BL) connected to this sense latch (SL). The storage cells proper are arranged in a semiconductor structure having a diffusion layer acting as a conductor and a multiple metal layer. The outputs of the sense latch (SL) are connected to two pairs of cross-coupled charge storge elements (BB) acting as bit line coupling transistors which are connected to extended partitioned bit line pairs (BL1, BL1', and BL2, BL2'). Each section has its own reference cells and is coupled to the sense latch (SL), the sections furthest from the sense latch are coupled through low-capacity metal lines, and charge coupling elements (BB). These metal sections of the bit lines meander over the surface of the semiconductor structure.

Abstract: A field effect transistor driver circuit responsive to a single input pusle generates a highly loadable output clock pulse with short rise and fall times, the rising edge being shifted relative to said input pulse by a controllable delay time but the trailing edge remaining practically undelayed. This advantageous pulse form is achieved through an improved controlling of a bootstrap output stage. Two preceding stages, i.e., a transmission gate and a delay stage supply two out-of-phase control pulses with high amplitudes and steep edges. Of essential importance is the novel delay stage which is designed as push-pull stage with a load FET and a driver FET. The gate of the load FET is controlled by the output pulse of the bootstrap stage 2 fed back via a third FET and by a capacitively coupled-in input pulse at the drain, whereas the gate of driver FET is controlled from the bootstrapped output of the transmission gate. The connecting point of load and driver FET represents the output of the delay stage.