Abstract: A method for forming a pixelated optoelectronic stack comprises forming a stacked layer structure that comprises a bottom electrode layer, an optoelectronic layer over the bottom electrode layer, and a patterned hard-mask comprising a pattern over the optoelectronic layer. The method comprises replicating the pattern into the optoelectronic layer and the bottom electrode layer, thereby forming a first intermediate pixelated stack comprising at least two islands of stack separated from one another by stack-free areas; providing an electrically insulating layer on the first intermediate pixelated stack; removing a top portion of the electrically insulating layer and removing any remaining hard-mask so that a top surface of the electrically insulating layer is coplanar with an exposed top surface of the first intermediate pixelated stack, yielding a second intermediate pixelated stack; and forming a top transparent electrode layer over the second intermediate pixelated stack.

Abstract: A method for forming a pixelated optoelectronic stack comprises forming a stacked layer structure that comprises a bottom electrode layer, an optoelectronic layer over the bottom electrode layer, and a patterned hard-mask comprising a pattern over the optoelectronic layer. The method comprises replicating the pattern into the optoelectronic layer and the bottom electrode layer, thereby forming a first intermediate pixelated stack comprising at least two islands of stack separated from one another by stack-free areas; providing an electrically insulating layer on the first intermediate pixelated stack; removing a top portion of the electrically insulating layer and removing any remaining hard-mask so that a top surface of the electrically insulating layer is coplanar with an exposed top surface of the first intermediate pixelated stack, yielding a second intermediate pixelated stack; and forming a top transparent electrode layer over the second intermediate pixelated stack.

Abstract: The present invention provides a method for capacitive detection of the presence of target sample on a substrate, which comprises the steps of: binding a target sample to selective binding sites on the substrate, the target sample being directly or indirectly labeled with conductive labels, and sensing the presence of the bound conductive labels to a binding site to thereby determine the presence of the target sample. The sensing step is carried out by a capacitive detection of the presence of the conductive labels. The present invention also provides a capacitive sensor device for determining the presence of a target sample. Conductive labels are directly or indirectly couplable to the target sample.

Abstract: The present invention provides an electronic transducer (10) and a method for detecting and/or characterizing target materials or physico-chemical stimuli in an external medium (8) using the electronic transducer (10). The electronic transducer (10) comprises a sensing element (3) featuring a variable conductance when exposed to a stimulus from the external medium and a first and second electrode (5a, 5b) spaced apart on or in a sensing material surface of a substrate, the sensing element being provided in or on the substrate and being located between the first and the second electrodes (5a, 5b) forming a pair of sensing electrodes for sensing a change in conductance of the sensing element (3) in a direction substantially parallel to the sensing material surface, at least one of the sensing electrodes (5a, 5b) being electrically insulated from the sensing element (3) by a dielectric layer (4), so as to be capacitively coupled to the sensing element (3).

Abstract: A semiconductor leadframe assembly (20A) and a method for manufacturing a semiconductor component (50) using the semiconductor leadframe assembly (20A). The semiconductor leadframe assembly (20A) includes a leadframe (10A) having flag portions (18A), lead portions (19A), and vias (14A). The vias (14A) serve as dielectric receiving areas. The assembly (20A) further includes semiconductor chips (21A) mounted on the flag portions (18A) and a dielectric material (33A) that covers the semiconductor chips (21A) and fills the vias (14A). The surface mount semiconductor component (50) is singulated from the semiconductor leadframe assembly (20A) to form electrical interconnects (18, 19) of the surface mount semiconductor component (50).