Patents by Inventor Luis Useche
Luis Useche has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10073721Abstract: Techniques and systems are disclosed for implementing non-blocking writes to eliminate the fetch-before-write requirement by creating an in-memory patch for the updated page and unblocking the calling process. Non-blocking writes eliminate such blocking by buffering the written data elsewhere in memory and unblocking the writing process immediately. Subsequent reads to the updated page locations are also made non-blocking and, in some cases, can be eliminated when the read request can be serviced from in-memory patches. Implementation scenarios can include an operating system (OS) enhancement, revision to an existing OS component (e.g., the OS kernel), special OS component, or enhancement to the software or firmware of the controller software or microcontroller of a storage device or array of storage devices.Type: GrantFiled: August 17, 2015Date of Patent: September 11, 2018Assignee: The Florida International University Board of TrusteesInventors: Raju Rangaswami, Daniel Campello, Luis Useche, Hector Lopez, Ricardo Koller
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Patent number: 9529534Abstract: Exemplary methods, apparatuses, and systems determine a miss-rate at various amounts of memory allocation for each of a plurality of workloads running within a computer. A value representing an estimated change in miss-rate for each of the workloads based upon an increase in a current allocation of memory to the workload is determined. The workload with a value representing a greatest improvement in hit rate is selected. Additional memory is allocated to the selected workload.Type: GrantFiled: June 13, 2014Date of Patent: December 27, 2016Assignee: VMware, Inc.Inventors: Sachin Manpathak, Mustafa Uysal, Puneet Zaroo, Luis Useche
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Patent number: 9329896Abstract: Exemplary methods, apparatuses, and systems receive a first request for a storage address at a first access time. Entries are added to first and second data structures. Each entry includes the storage address and the first access time. The first data structure is sorted in an order of storage addresses. The second data structure is sorted in an order of access times. A second request for the storage address is received at a second access time. The first access time is determined by looking up the entry in first data structure using the storage address received in the second request. The entry in the second data structure is looked up using the determined first access time. A number of entries in second data structure that were subsequent to the second entry is determined. A hit count for a reuse distance corresponding to the determined number of entries is incremented.Type: GrantFiled: June 13, 2014Date of Patent: May 3, 2016Assignee: VMware, Inc.Inventors: Sachin Manpathak, Mustafa Uysal, Puneet Zaroo, Ricardo Koller, Luis Useche
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Publication number: 20160055084Abstract: Techniques and systems are disclosed for implementing non-blocking writes to eliminate the fetch-before-write requirement by creating an in-memory patch for the updated page and unblocking the calling process. Non-blocking writes eliminate such blocking by buffering the written data elsewhere in memory and unblocking the writing process immediately. Subsequent reads to the updated page locations are also made non-blocking and, in some cases, can be eliminated when the read request can be serviced from in-memory patches. Implementation scenarios can include an operating system (OS) enhancement, revision to an existing OS component (e.g., the OS kernel), special OS component, or enhancement to the software or firmware of the controller software or microcontroller of a storage device or array of storage devices.Type: ApplicationFiled: August 17, 2015Publication date: February 25, 2016Applicant: The Florida International University Board of TrusteesInventors: Raju RANGASWAMI, Daniel CAMPELLO, Luis USECHE, Hector LOPEZ, Ricardo KOLLER
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Patent number: 9262192Abstract: Systems and techniques are described for allocating data store queues to virtual machines. A described technique includes allocating a respective queue to each of a plurality of threads, wherein the queue is configured to queue data requests from the respective thread and for a first data store, determining, for each of a plurality of threads, a respective maximum quantity of pending requests for the thread, wherein a quantity of pending requests sent from the respective queue to the first data store is equal to the maximum quantity of pending requests determined for the thread, determining, for each of the threads, a respective current quantity of operations per second, determining, for each of one or more first threads in the plurality of threads, a respective updated quantity of pending requests, and adjusting, for each first thread, the quantity of pending requests of the first thread sent to the first data store.Type: GrantFiled: March 14, 2014Date of Patent: February 16, 2016Assignee: VMware, Inc.Inventors: Ajay Gulati, Sachin Manpathak, Mustafa Uysal, Luis Useche
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Publication number: 20150363236Abstract: Exemplary methods, apparatuses, and systems receive a first request for a storage address at a first access time. Entries are added to first and second data structures. Each entry includes the storage address and the first access time. The first data structure is sorted in an order of storage addresses. The second data structure is sorted in an order of access times. A second request for the storage address is received at a second access time. The first access time is determined by looking up the entry in first data structure using the storage address received in the second request. The entry in the second data structure is looked up using the determined first access time. A number of entries in second data structure that were subsequent to the second entry is determined. A hit count for a reuse distance corresponding to the determined number of entries is incremented.Type: ApplicationFiled: June 13, 2014Publication date: December 17, 2015Inventors: SACHIN MANPATHAK, MUSTAFA UYSAL, PUNEET ZAROO, RICARDO KOLLER, LUIS USECHE
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Publication number: 20150363117Abstract: Exemplary methods, apparatuses, and systems determine a miss-rate at various amounts of memory allocation for each of a plurality of workloads running within a computer. A value representing an estimated change in miss-rate for each of the workloads based upon an increase in a current allocation of memory to the workload is determined. The workload with a value representing a greatest improvement in hit rate is selected. Additional memory is allocated to the selected workload.Type: ApplicationFiled: June 13, 2014Publication date: December 17, 2015Inventors: SACHIN MANPATHAK, MUSTAFA UYSAL, PUNEET ZAROO, LUIS USECHE
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Publication number: 20150169341Abstract: Systems and techniques are described for allocating data store queues to virtual machines. A described technique includes allocating a respective queue to each of a plurality of threads, wherein the queue is configured to queue data requests from the respective thread and for a first data store, determining, for each of a plurality of threads, a respective maximum quantity of pending requests for the thread, wherein a quantity of pending requests sent from the respective queue to the first data store is equal to the maximum quantity of pending requests determined for the thread, determining, for each of the threads, a respective current quantity of operations per second, determining, for each of one or more first threads in the plurality of threads, a respective updated quantity of pending requests, and adjusting, for each first thread, the quantity of pending requests of the first thread sent to the first data store.Type: ApplicationFiled: March 14, 2014Publication date: June 18, 2015Applicant: VMware, Inc.Inventors: Ajay Gulati, Sachin Manpathak, Mustafa Uysal, Luis Useche